參數(shù)資料
型號: SC16C850LIBS
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 1.8 V single UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode parallel bus interface
封裝: SC16C850LIB<SOT313|<<<1<Always Pb-free,;SC16C850LIB<SOT313|<<<1<Always Pb-free,;SC16C850LIB<SOT313|<<<1<Always Pb-free,;SC16C850LIBS<SOT617-1 (HVQFN3
文件頁數(shù): 34/55頁
文件大小: 1029K
代理商: SC16C850LIBS
SC16C850L
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 1 February 2011
34 of 55
NXP Semiconductors
SC16C850L
1.8 V single UART with 128-byte FIFOs and IrDA encoder/decoder
[1]
For 32-byte FIFO mode, refer to
Section 7.3
.
7.17 Flow Control Trigger Level High (FLWCNTH)
This 8-bit register is used to store the receive FIFO high threshold levels to start/stop
transmission during hardware/software flow control.
Table 27
shows the FLWCNTH
register bit settings; see
Section 6.5
.
Table 27.
Bit
7:0
[1]
For 32-byte FIFO mode, refer to
Section 7.3
.
7.18 Flow Control Trigger Level Low (FLWCNTL)
This 8-bit register is used to store the receive FIFO low threshold levels to start/stop
transmission during hardware/software flow control.
Table 28
shows the FLWCNTL
register bit settings; see
Section 6.5
.
Table 28.
Bit
7:0
[1]
For 32-byte FIFO mode, refer to
Section 7.3
.
7.19 Clock Prescaler (CLKPRES)
This register hold values for the clock prescaler.
Table 29.
Bit
7:4
3:0
FLWCNTH register bits description
Symbol
FLWCNTH[7:0]
Description
This register stores the programmable HIGH threshold level for
hardware and software flow control for 128-byte FIFO mode
[1]
.
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
FLWCNTL register bits description
Symbol
FLWCNTL[7:0]
Description
This register stores the programmable LOW threshold level for
hardware and software flow control for 128-byte FIFO mode
[1]
.
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
Clock Prescaler register bits description
Symbol
Description
CLKPRES[7:4]
reserved
CLKPRES[3:0]
Clock Prescaler value. Reset to 0.
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