參數(shù)資料
型號: SC16C850LIBS
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 1.8 V single UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode parallel bus interface
封裝: SC16C850LIB<SOT313|<<<1<Always Pb-free,;SC16C850LIB<SOT313|<<<1<Always Pb-free,;SC16C850LIB<SOT313|<<<1<Always Pb-free,;SC16C850LIBS<SOT617-1 (HVQFN3
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代理商: SC16C850LIBS
SC16C850L
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NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 1 February 2011
33 of 55
NXP Semiconductors
SC16C850L
1.8 V single UART with 128-byte FIFOs and IrDA encoder/decoder
Table 24.
Cont-3
0
1
0
1
X
X
X
1
[1]
When using a software flow control the Xon/Xoff characters cannot be used for data transfer.
7.15 Transmit Interrupt Level Register (TXINTLVL)
This 8-bit register is used to store the transmit FIFO trigger levels used for interrupt
generation. Trigger levels from 1 to 128 can be programmed with a granularity of 1.
Table 25
shows the TXINTLVL register bit settings.
Table 25.
Bit
7:0
[1]
For 32-byte FIFO mode, refer to
Section 7.3
.
7.16 Receive Interrupt Level Register (RXINTLVL)
This 8-bit register is used store the receive FIFO trigger levels used for interrupt
generation. Trigger levels from 1 to 128 can be programmed with a granularity of 1.
Table 26
shows the RXINTLVL register bit settings.
Table 26.
Bit
7:0
Software flow control functions
[1]
Cont-2
Cont-1
0
X
0
X
1
X
1
X
X
0
X
1
X
0
0
1
Cont-0
X
X
X
X
0
0
1
1
TX, RX software flow controls
No transmit flow control
Transmit Xon1/Xoff1
Transmit Xon2/Xoff2
Transmit Xon1 and Xon2/Xoff1 and Xoff2
No receive flow control
Receiver compares Xon1/Xoff1
Receiver compares Xon2/Xoff2
Transmit Xon1/Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
Transmit Xon2/Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
Transmit Xon1 and Xon2, Xoff1 and Xoff2
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
0
1
1
1
1
1
1
1
TXINTLVL register bits description
Symbol
Description
TXINTLVL[7:0]
This register stores the programmable transmit interrupt trigger levels
for 128-byte FIFO mode
[1]
.
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
RXINTLVL register bits description
Symbol
Description
RXINTLVL[7:0]
This register stores the programmable receive interrupt trigger levels
for 128-byte FIFO mode
[1]
.
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
相關(guān)PDF資料
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SC16C850LIET 1.8 V single UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode parallel bus interface
SC16C850SVIBS 1.8 V single UART, 20 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA), and XScale VLIO bus interface
SC16C850VIBS 1.8 V single UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA), and XScale VLIO bus interface
SC16C852LIB 1.8 V dual UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode bus interface
SC16C852LIBS 1.8 V dual UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode bus interface
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