參數(shù)資料
型號: SC16C850LIB
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 1.8 V single UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode parallel bus interface
封裝: SC16C850LIB<SOT313|<<<1<Always Pb-free,;SC16C850LIB<SOT313|<<<1<Always Pb-free,;SC16C850LIB<SOT313|<<<1<Always Pb-free,;SC16C850LIBS<SOT617-1 (HVQFN3
文件頁數(shù): 55/55頁
文件大?。?/td> 1029K
代理商: SC16C850LIB
NXP Semiconductors
SC16C850L
1.8 V single UART with 128-byte FIFOs and IrDA encoder/decoder
NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 1 February 2011
Document identifier: SC16C850L
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1
2
3
4
5
5.1
5.2
6
6.1
6.2
6.3
6.4
6.4.1
6.4.2
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.11.1
6.11.2
6.12
6.13
6.13.1
6.13.2
6.13.3
6.13.3.1 Normal Multi-drop mode. . . . . . . . . . . . . . . . . 19
6.13.3.2 Auto address detection. . . . . . . . . . . . . . . . . . 20
7
Register descriptions . . . . . . . . . . . . . . . . . . . 20
7.1
Transmit (THR) and Receive (RHR)
Holding Registers . . . . . . . . . . . . . . . . . . . . . . 23
7.2
Interrupt Enable Register (IER) . . . . . . . . . . . 23
7.2.1
IER versus Transmit/Receive FIFO
interrupt mode operation . . . . . . . . . . . . . . . . 24
7.2.2
IER versus Receive/Transmit FIFO
polled mode operation . . . . . . . . . . . . . . . . . . 24
7.3
FIFO Control Register (FCR) . . . . . . . . . . . . . 25
7.3.1
FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.4
Interrupt Status Register (ISR) . . . . . . . . . . . . 26
7.5
Line Control Register (LCR) . . . . . . . . . . . . . . 27
7.6
Modem Control Register (MCR). . . . . . . . . . . 28
7.7
Line Status Register (LSR). . . . . . . . . . . . . . . 29
7.8
Modem Status Register (MSR). . . . . . . . . . . . 30
7.9
Extra Feature Control Register (EFCR) . . . . . 31
7.10
Scratchpad Register (SPR) . . . . . . . . . . . . . . 31
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . . 9
UART selection. . . . . . . . . . . . . . . . . . . . . . . . . 9
Extended mode (128-byte FIFO) . . . . . . . . . . 10
Internal registers. . . . . . . . . . . . . . . . . . . . . . . 10
FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 11
32-byte FIFO mode . . . . . . . . . . . . . . . . . . . . 11
128-byte FIFO mode . . . . . . . . . . . . . . . . . . . 11
Hardware flow control. . . . . . . . . . . . . . . . . . . 12
Software flow control . . . . . . . . . . . . . . . . . . . 12
Special character detect . . . . . . . . . . . . . . . . . 13
Interrupt priority and time-out interrupts . . . . . 13
Programmable baud rate generator . . . . . . . . 14
Loopback mode . . . . . . . . . . . . . . . . . . . . . . . 16
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Conditions to enter Sleep mode . . . . . . . . . . . 18
Conditions to resume normal operation . . . . . 18
Low power feature . . . . . . . . . . . . . . . . . . . . . 18
RS-485 features . . . . . . . . . . . . . . . . . . . . . . . 19
Auto RS-485 RTS control. . . . . . . . . . . . . . . . 19
RS-485 RTS inversion . . . . . . . . . . . . . . . . . . 19
Auto 9-bit mode (RS-485). . . . . . . . . . . . . . . . 19
7.11
7.12
7.13
7.14
7.15
7.16
7.17
7.18
7.19
7.20
Divisor Latch (DLL and DLM). . . . . . . . . . . . . 31
Transmit FIFO Level Count (TXLVLCNT) . . . 31
Receive FIFO Level Count (RXLVLCNT). . . . 31
Enhanced Feature Register (EFR) . . . . . . . . 32
Transmit Interrupt Level Register (TXINTLVL) 33
Receive Interrupt Level Register (RXINTLVL) 33
Flow Control Trigger Level High (FLWCNTH) 34
Flow Control Trigger Level Low (FLWCNTL) . 34
Clock Prescaler (CLKPRES) . . . . . . . . . . . . . 34
RS-485 Turn-around Time Delay
(RS485TIME). . . . . . . . . . . . . . . . . . . . . . . . . 35
Advanced Feature Control Register 2
(AFCR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Advanced Feature Control Register 1
(AFCR1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
SC16C850L external reset condition
and software reset . . . . . . . . . . . . . . . . . . . . . 37
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 38
Static characteristics . . . . . . . . . . . . . . . . . . . 38
Dynamic characteristics. . . . . . . . . . . . . . . . . 39
Timing diagrams. . . . . . . . . . . . . . . . . . . . . . . 41
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 47
Soldering of SMD packages. . . . . . . . . . . . . . 49
Introduction to soldering. . . . . . . . . . . . . . . . . 49
Wave and reflow soldering. . . . . . . . . . . . . . . 49
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 49
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 50
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 51
Revision history . . . . . . . . . . . . . . . . . . . . . . . 52
Legal information . . . . . . . . . . . . . . . . . . . . . . 53
Data sheet status. . . . . . . . . . . . . . . . . . . . . . 53
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Contact information . . . . . . . . . . . . . . . . . . . . 54
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7.21
7.22
7.23
8
9
10
10.1
11
12
12.1
12.2
12.3
12.4
13
14
15
15.1
15.2
15.3
15.4
16
17
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