參數(shù)資料
型號(hào): SC16C754BIB80
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit-s (max.) with 64-byte FIFOs
封裝: SC16C754BIA68<SOT188-2 (PLCC68)|<<http://www.nxp.com/packages/SOT188-2.html<1<Always Pb-free,;SC16C754BIA68<SOT188-2 (PLCC68)|<<http://www.nxp.com/packages/SOT188-2.html&
文件頁(yè)數(shù): 37/51頁(yè)
文件大?。?/td> 253K
代理商: SC16C754BIB80
SC16C754B_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 6 October 2008
37 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
11. Dynamic characteristics
Table 26.
T
amb
=
40
°
C to +85
°
C; tolerance of V
CC
±
10 %, unless otherwise specified.
Symbol Parameter
Dynamic characteristics
Conditions
V
CC
= 2.5 V
Min
10
10
-
0
0
10
90
0
20
-
-
10
20
0
25
20
15
-
-
V
CC
= 3.3 V
Min
6
6
-
0
0
10
26
0
20
-
-
10
20
0
25
15
5
-
-
V
CC
= 5.0 V
Min
6
6
Unit
Max
-
-
48
-
-
-
-
-
-
90
15
-
-
-
-
-
-
100
100
Max
-
-
80
-
-
-
-
-
-
26
15
-
-
-
-
-
-
33
24
Max
-
-
80
-
-
-
-
-
-
23
15
-
-
-
-
-
-
29
23
t
WL
t
WH
f
XTAL
t
6s
t
6h
t
7d
t
7w
t
7h
t
9d
t
12d
t
12h
t
13d
t
13w
t
13h
t
15d
t
16s
t
16h
t
17d
t
18d
pulse width LOW
pulse width HIGH
oscillator/clock frequency
address set-up time
address hold time
IOR delay from chip select
IOR strobe width
chip select hold time from IOR
read cycle delay
delay from IOR to data
data disable time
IOW delay from chip select
IOW strobe width
chip select hold time from IOW
write cycle delay
data set-up time
data hold time
delay from IOW to output
delay to set interrupt from
Modem input
delay to reset interrupt from
IOR
delay from stop to set interrupt
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[1][2]
0
0
10
23
0
20
-
-
10
15
0
20
15
5
-
-
25 pF load
25 pF load
25 pF load
25 pF load
25 pF load
25 pF load
t
19d
25 pF load
-
100
-
24
-
23
ns
t
20d
-
1T
RCLK
[3]
-
1T
RCLK
[3]
-
1T
RCLK
[3]
ns
t
21d
delay from IOR to reset
interrupt
delay from start to set interrupt
delay from IOW to transmit start
25 pF load
-
100
-
29
-
28
ns
t
22d
t
23d
-
100
-
45
-
40
ns
ns
8T
RCLK
[3]
24T
RCLK
[3]
8T
RCLK
[3]
24T
RCLK
[3]
8T
RCLK
[3]
24T
RCLK
[3]
t
24d
delay from IOW to reset
interrupt
delay from stop to set RXRDY
-
100
-
45
-
40
ns
t
25d
-
1T
RCLK
[3]
-
1T
RCLK
[3]
-
1T
RCLK
[3]
ns
t
26d
t
27d
t
28d
delay from IOR to reset RXRDY
delay from IOW to set TXRDY
delay from start to reset TXRDY
-
-
-
100
100
8T
RCLK
[3]
-
-
-
45
45
-
-
-
40
40
ns
ns
ns
8T
RCLK
[3]
8T
RCLK
[3]
t
RESET
N
RESET pulse width
baud rate divisor
[4]
200
1
-
200
1
-
200
1
-
ns
(2
16
1)
(2
16
1)
(2
16
1)
相關(guān)PDF資料
PDF描述
SC16C754BIBM 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit-s (max.) with 64-byte FIFOs
SC16C850IBS 2.5 V to 3.3 V UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA), and 16 mode or 68 mode parallel bus interface
SC16C850IET 2.5 V to 3.3 V UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA), and 16 mode or 68 mode parallel bus interface
SC16C850LIB 1.8 V single UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode parallel bus interface
SC16C850LIBS 1.8 V single UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode parallel bus interface
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