參數(shù)資料
型號(hào): SC16C754BIB80
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit-s (max.) with 64-byte FIFOs
封裝: SC16C754BIA68<SOT188-2 (PLCC68)|<<http://www.nxp.com/packages/SOT188-2.html<1<Always Pb-free,;SC16C754BIA68<SOT188-2 (PLCC68)|<<http://www.nxp.com/packages/SOT188-2.html&
文件頁(yè)數(shù): 27/51頁(yè)
文件大?。?/td> 253K
代理商: SC16C754BIB80
SC16C754B_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 6 October 2008
27 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
7.6 Modem Control Register (MCR)
The MCR controls the interface with the modem, data set, or peripheral device that is
emulating the modem.
Table 14
shows modem control register bit settings.
[1]
MCR[7:5] can only be modified when EFR[4] is set, that is, EFR[4] is a write enable.
Table 14.
Bit
7
Modem control register bits description
Symbol
Description
MCR[7]
[1]
Clock select.
logic 0 = divide-by-1 clock input
logic 1 = divide-by-4 clock input
MCR[6]
[1]
TCR and TLR enable.
logic 0 = no action
logic 1 = enable access to the TCR and TLR registers
MCR[5]
[1]
Xon Any.
logic 0 = disable Xon Any function
logic 1 = enable Xon Any function
MCR[4]
Enable loopback.
logic 0 = normal operating mode
logic 1 = enable local loopback mode (internal). In this mode the
MCR[3:0] signals are looped back into MSR[7:4] and the TX output is
looped back to the RX input internally.
MCR[3]
IRQ enable OP.
logic 0 = forces INTA to INTD outputs to the 3-state mode and OP
output to HIGH state
logic 1 = forces the INTA to INTD outputs to the active state and OP
output to LOW state. In loopback mode, controls MSR[7].
MCR[2]
FIFO Ready enable.
logic 0 = disable the FIFO Rdy register
logic 1 = enable the FIFO Rdy register. In loopback mode, controls
MSR[6].
MCR[1]
RTS
logic 0 = force RTS output to inactive (HIGH)
logic 1 = force RTS output to active (LOW). In loopback mode, controls
MSR[4]. If auto-RTS is enabled, the RTS output is controlled by
hardware flow control.
MCR[0]
DTR
logic 0 = force DTR output to inactive (HIGH)
logic 1 = force DTR output to active (LOW). In loopback mode, controls
MSR[5].
6
5
4
3
2
1
0
相關(guān)PDF資料
PDF描述
SC16C754BIBM 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit-s (max.) with 64-byte FIFOs
SC16C850IBS 2.5 V to 3.3 V UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA), and 16 mode or 68 mode parallel bus interface
SC16C850IET 2.5 V to 3.3 V UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA), and 16 mode or 68 mode parallel bus interface
SC16C850LIB 1.8 V single UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode parallel bus interface
SC16C850LIBS 1.8 V single UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode parallel bus interface
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