參數(shù)資料
型號: SC16C752BIBS
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit-s (max.), with 64-byte FIFOs
封裝: SC16C752BIB48<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html<1<Always Pb-free,;SC16C752BIB48<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html&
文件頁數(shù): 28/47頁
文件大?。?/td> 945K
代理商: SC16C752BIBS
SC16C752B
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NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 6 — 30 November 2010
28 of 47
NXP Semiconductors
SC16C752B
5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
7.9 Interrupt Identification Register (IIR)
The IIR is a read-only 8-bit register which provides the source of the interrupt in a
prioritized manner.
Table 17
shows Interrupt Identification Register bit settings.
Table 17.
Bit
7:6
5
4
3:1
0
The interrupt priority list is shown in
Table 18
.
Table 18.
Priority
level
1
2
2
3
4
5
7.10 Enhanced Feature Register (EFR)
This 8-bit register enables or disables the enhanced features of the UART.
Table 19
shows the Enhanced Feature Register bit settings.
Table 19.
Bit
7
Interrupt Identification Register bits description
Symbol
Description
IIR[7:6]
Mirror the contents of FCR[0]
IIR[5]
RTSn/CTSn LOW-to-HIGH change of state
IIR[4]
1 = Xoff/Special character has been detected
IIR[3:1]
3-bit encoded interrupt. See
Table 18
.
IIR[0]
Interrupt status.
logic 0 = an interrupt is pending
logic 1 = no interrupt is pending
Interrupt priority list
IIR[5]
IIR[4]
IIR[3]
IIR[2]
IIR[1]
IIR[0]
Source of the interrupt
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
1
1
1
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
Receiver Line Status error
Receiver time-out interrupt
RHR interrupt
THR interrupt
Modem interrupt
Received Xoff signal/ special
character
CTSn, RTSn change of state from
active (LOW) to inactive (HIGH)
6
1
0
0
0
0
0
Enhanced Feature Register bits description
Symbol
Description
EFR[7]
CTS flow control enable.
logic 0 = CTS flow control is disabled (normal default condition)
logic 1 = CTS flow control is enabled. Transmission will stop when a HIGH
signal is detected on the CTSn pin.
EFR[6]
RTS flow control enable.
logic 0 = RTS flow control is disabled (normal default condition)
logic 1 = RTS flow control is enabled. The RTSn pin goes HIGH when the
receiver FIFO
halt
trigger level TCR[3:0] is reached, and goes LOW when the
receiver FIFO
resume
transmission trigger level TCR[7:4] is reached.
6
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SC16C752BIBS,157 功能描述:UART 接口集成電路 16CB 2.5V-5V 2CH RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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SC16C752BIBS-S 功能描述:UART 接口集成電路 2CH. UART 64B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel