參數(shù)資料
型號： SC16C752BIBS
廠商： NXP Semiconductors N.V.
元件分類： 收發(fā)器
英文描述： 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit-s (max.), with 64-byte FIFOs
封裝： SC16C752BIB48<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html<1<Always Pb-free,;SC16C752BIB48<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html&
文件頁數(shù)： 20/47頁
文件大小： 945K
代理商： SC16C752BIBS
SC16C752B
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 6 — 30 November 2010
20 of 47
NXP Semiconductors
SC16C752B
5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Table 10
lists and describes the SC16C752B internal registers.
[1]
These registers are accessible only when LCR[7] = logic 0.
[2]
These bits can only be modified if register bit EFR[4] is enabled, i.e., if enhanced functions are enabled.
[3]
The Special register set is accessible only when LCR[7] is set to a logic 1.
[4]
Enhanced Feature Register; Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to BFh.
Table 10.
SC16C752B internal registers
A2 A1 A0 Register Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read/
Write
General register set
[1]
0
0
0
0
0
0
0
0
1
RHR
THR
IER
bit 7
bit 7
0/CTS
interrupt
enable
[2]
RX trigger
level
(MSB)
bit 6
bit 6
0/RTS
interrupt
enable
[2]
RX trigger
level (LSB)
bit 5
bit 5
0/Xoff
[2]
bit 4
bit 4
0/X sleep
mode
[2]
bit 3
bit 3
modem
status
interrupt
DMA
mode
select
bit 2
bit 2
receive
line status
interrupt
TX FIFO
reset
bit 1
bit 1
THR
empty
interrupt
RX FIFO
reset
bit 0
bit 0
Rx data
available
interrupt
FIFO
enable
R
W
R/W
0
1
0
FCR
0/TX
trigger
level
(MSB)
[2]
0/CTS,
RTS
0/TX
trigger
level
(LSB)
[2]
0/Xoff
W
0
1
0
IIR
FCR[0]
FCR[0]
interrupt
priority
bit 2
parity
enable
interrupt
priority
bit 1
number of
stop bits
interrupt
priority
bit 0
word
length
bit 1
RTS
interrupt
status
R
0
1
1
LCR
DLAB
break
control bit
set parity
parity type
select
word
length
bit 0
DTR
R/W
1
0
0
MCR
1
×
or
1
×
/ 4
clock
[2]
0/error in
RX FIFO
CD
bit 7
bit 7
bit 7
0
TCR and
TLR
enable
[2]
THR and
TSR empty
RI
bit 6
bit 6
bit 6
0
0/Xon
Any
[2]
0/enable
loopback
IRQ
enable
OP
framing
error
Δ
CD
bit 3
bit 3
bit 3
0
FIFO
ready
enable
parity
error
Δ
RI
bit 2
bit 2
bit 2
0
R/W
1
0
1
LSR
THR
empty
DSR
bit 5
bit 5
bit 5
RX FIFO
B status
break
interrupt
CTS
bit 4
bit 4
bit 4
RX FIFO
A status
overrun
error
Δ
DSR
bit 1
bit 1
bit 1
TX FIFO
B status
data in
receiver
Δ
CTS
bit 0
bit 0
bit 0
TX FIFO
A status
R
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
MSR
SPR
TCR
TLR
FIFO
Rdy
R
R/W
R/W
R/W
R
Special register set
[3]
0
0
0
0
0
1
Enhanced register set
[4]
0
1
0
DLL
DLM
bit 7
bit 15
bit 6
bit 14
bit 5
bit 13
bit 4
bit 12
bit 3
bit 11
bit 2
bit 10
bit 1
bit 9
bit 0
bit 8
R/W
R/W
EFR
auto CTS
auto RTS
Special
character
detect
Enable
IER[7:4],
FCR[5:4],
MCR[7:5]
bit 4
bit 4
bit 4
bit 4
software
flow
control
bit 3
bit 3
bit 3
bit 3
bit 3
software
flow
control
bit 2
bit 2
bit 2
bit 2
bit 2
software
flow
control
bit 1
bit 1
bit 1
bit 1
bit 1
software
flow
control
bit 0
bit 0
bit 0
bit 0
bit 0
R/W
1
1
1
1
0
0
1
1
0
1
0
1
Xon1
Xon2
Xoff1
Xoff2
bit 7
bit 7
bit 7
bit 7
bit 6
bit 6
bit 6
bit 6
bit 5
bit 5
bit 5
bit 5
R/W
R/W
R/W
R/W
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