參數(shù)資料
型號(hào): SC16C652BIB48,151
廠商: NXP Semiconductors
文件頁數(shù): 4/21頁
文件大?。?/td> 0K
描述: IC UART DUAL W/FIFO 48-LQFP
產(chǎn)品培訓(xùn)模塊: Stand-Alone UARTs
標(biāo)準(zhǔn)包裝: 250
特點(diǎn): 2 通道
通道數(shù): 2,DUART
FIFO's: 32 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 托盤
產(chǎn)品目錄頁面: 827 (CN2011-ZH PDF)
其它名稱: 568-3276
935274409151
SC16C652BIB48-S
SC16C652B_4
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 1 September 2005
12 of 43
Philips Semiconductors
SC16C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
6.9 DMA operation
The SC16C652B FIFO trigger level provides additional exibility to the user for block
mode operation. The user can optionally operate the transmit and receive FIFOs in the
DMA mode (FCR[3]). The DMA mode affects the state of the RXRDY and TXRDY output
pins. Table 7 and Table 8 show this.
6.10 Loop-back mode
The internal loop-back capability allows on-board diagnostics. In the loop-back mode, the
normal modem interface pins are disconnected and recongured for loop-back internally
(see Figure 5). MCR[3:0] register bits are used for controlling loop-back diagnostic testing.
In the loop-back mode, the transmitter output (TX) and the receiver input (RX) are
disconnected from their associated interface pins, and instead are connected together
internally. The CTS, DSR, CD, and RI are disconnected from their normal modem control
inputs pins, and instead are connected internally to RTS, DTR, MCR[3] (OP2) and
Table 6:
Baud rate generator programming table using a 1.8432 MHz clock
Output
baud rate
(bit/s)
Output
16
× clock divisor
(decimal)
Output
16
× clock divisor
(HEX)
DLM
program value
(HEX)
DLL
program value
(HEX)
50
2304
900
09
00
75
1536
600
06
00
110
1047
417
04
17
150
768
300
03
00
300
384
180
01
80
600
192
C0
00
C0
1200
96
60
00
60
2400
48
30
00
30
3600
32
20
00
20
4800
24
18
00
18
7200
16
10
00
10
9600
12
0C
00
0C
19.2 k
6
06
00
06
38.4 k
3
03
00
03
57.6 k
2
02
00
02
115.2 k
1
01
00
01
Table 7:
Effect of DMA mode on state of RXRDY pin
Non-DMA mode
DMA mode
1 = FIFO empty
0-to-1 transition when FIFO empties
0 = at least 1 byte in FIFO
1-to-0 transition when FIFO reaches trigger level, or time-out occurs
Table 8:
Effect of DMA mode on state of TXRDY pin
Non-DMA mode
DMA mode
1 = at least 1 byte in FIFO
0-to-1 transition when FIFO becomes full
0 = FIFO empty
1-to-0 transition when FIFO goes below trigger level
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