- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄3764 > SC16C652BIB48,151 (NXP Semiconductors)IC UART DUAL W/FIFO 48-LQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | SC16C652BIB48,151 |
| 廠商： | NXP Semiconductors |
| 文件頁(yè)數(shù)： | 2/21頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC UART DUAL W/FIFO 48-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Stand-Alone UARTs |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 特點(diǎn)： | 2 通道 |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 32 字節(jié) |
| 電源電壓： | 2.5V，3.3V，5V |
| 帶自動(dòng)流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動(dòng)位檢測(cè)功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁(yè)面： | 827 (CN2011-ZH PDF) |
| 其它名稱： | 568-3276 935274409151 SC16C652BIB48-S |
第1頁(yè)當(dāng)前第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)
SC16C652B_4
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 1 September 2005
10 of 43
Philips Semiconductors
SC16C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
Reset initially sets the contents of the Xon/Xoff 8-bit ow control registers to a logic 0.
Following reset, the user can write any Xon/Xoff value desired for software ow control.
Different conditions can be set to detect Xon/Xoff characters and suspend/resume
transmissions. When double 8-bit Xon/Xoff characters are selected, the SC16C652B
compares two consecutive receive characters with two software ow control 8-bit values
(Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above
described ow control mechanisms, ow control characters are not placed (stacked) in the
user accessible RX data buffer or FIFO. When using a software ow control the Xon/Xoff
characters cannot be used for data transfer.
In the event that the receive buffer is overlling and ow control needs to be executed, the
SC16C652B automatically sends an Xoff message (when enabled) via the serial TX
output to the remote modem. The SC16C652B sends the Xoff1/Xoff2 characters as soon
as received data passes the programmed trigger level. To clear this condition, the
SC16C652B will transmit the programmed Xon1/Xon2 characters as soon as receive data
drops below the programmed trigger level.
6.6 Special feature software ow control
A special feature is provided to detect an 8-bit character when EFR[5] is set. When 8-bit
character is detected, it will be placed on the user-accessible data stack along with normal
incoming RX data. This condition is selected in conjunction with EFR[3:0]. Note that
software ow control should be turned off when using this special mode by setting
EFR[3:0] to a logic 0.
The SC16C652B compares each incoming receive character with Xoff2 data. If a match
exists, the received data will be transferred to the FIFO, and ISR[4] will be set to indicate
detection of a special character. Although Table 9 “SC16C652B internal registers” shows
each X-Register with eight bits of character information, the actual number of bits is
dependent on the programmed word length. Line Control Register bits LCR[1:0] dene the
number of character bits, that is, either 5 bits, 6 bits, 7 bits or 8 bits. The word length
selected by LCR[1:0] also determine the number of bits that will be used for the special
character comparison. Bit 0 in the X-registers corresponds with the LSB bit for the receive
character.
6.7 Hardware/software and time-out interrupts
The interrupts are enabled by IER[3:0]. Care must be taken when handling these
interrupts. Following a reset, if Interrupt Enable Register (IER) bit 1 = 1, the SC16C652B
will issue a Transmit Holding Register interrupt. This interrupt must be serviced prior to
continuing operations. The ISR provides the current singular highest priority interrupt only.
It could be noted that CTS and RTS interrupts have lowest interrupt priority. A condition
can exist where a higher priority interrupt may mask the lower priority CTS/RTS
interrupt(s). Only after servicing the higher pending interrupt will the lower priority
CTS/RTS interrupt(s) be reected in the status register. Servicing the interrupt without
investigating further interrupt conditions can result in data errors.
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time Out have the same interrupt
priority (when enabled by IER[0]). The receiver issues an interrupt after the number of
characters have reached the programmed trigger level. In this case, the SC16C652B
FIFO may hold more characters than the programmed trigger level. Following the removal
of a data byte, the user should re-check LSR[0] for additional characters. A Receive
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SC16C652BIB48,128 | IC ENCODER/DECODER IRDA 48LQFP |
| SCC2691AC1N24,602 | IC UART SINGLE 24-DIP |
| SCC2691AE1N24,129 | IC UART 24-DIP |
| SCC2691AE1N24,602 | IC UART SINGLE 24-DIP |
| SC16C2550BIB48,151 | IC UART DUAL W/FIFO 48-LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SC16C652BIB48-F | 功能描述:UART 接口集成電路 16CB 2.5V-5V 2CH UART 32B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C652BIB48-S | 制造商:NXP Semiconductors 功能描述:UART 2-CH 32Byte FIFO 2.5V/3.3V/5V 48-Pin LQFP Tray |
| SC16C652BIBS | 功能描述:UART 接口集成電路 16CB 2.5V-5V 2CH UART 32B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C652BIBS,128 | 功能描述:UART 接口集成電路 16CB 2.5V-5V 2CH RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C652BIBS,151 | 功能描述:UART 接口集成電路 16CB 2.5V-5V 2CH RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。