參數(shù)資料
型號: SC16C652BIB48,151
廠商: NXP Semiconductors
文件頁數(shù): 17/21頁
文件大?。?/td> 0K
描述: IC UART DUAL W/FIFO 48-LQFP
產(chǎn)品培訓模塊: Stand-Alone UARTs
標準包裝: 250
特點: 2 通道
通道數(shù): 2,DUART
FIFO's: 32 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應商設備封裝: 48-LQFP(7x7)
包裝: 托盤
產(chǎn)品目錄頁面: 827 (CN2011-ZH PDF)
其它名稱: 568-3276
935274409151
SC16C652BIB48-S
SC16C652B_4
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 1 September 2005
5 of 43
Philips Semiconductors
SC16C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
5.2 Pin description
Table 2:
Pin description
Symbol
Pin
Type Description
LQFP48 HVQFN32
A0
28
19
I
Address 0 select bit. Internal register address selection.
A1
27
18
I
Address 1 select bit. Internal register address selection.
A2
26
17
I
Address 2 select bit. Internal register address selection.
CDA40
-
I
Carrier Detect (active LOW). These inputs are associated with individual UART
channels A through B. A logic 0 on this pin indicates that a carrier has been
detected by the modem for that channel.
CDB
16
-
CSA
10
8
I
Chip Select A, B (active LOW). This function is associated with individual
channels, A through B. These pins enable data transfers between the user CPU
and the SC16C652B for the channel(s) addressed. Individual UART sections (A, B)
are addressed by providing a logic 0 on the respective CSA, CSB pin.
CSB
11
9
CTSA
38
25
I
Clear to Send (active LOW). These inputs are associated with individual UART
channels, A through B. A logic 0 on the CTS pin indicates the modem or data set is
ready to accept transmit data from the SC16C652B. Status can be tested by
reading MSR[4]. This pin has no effect on the UART’s transmit or receive
operation.
CTSB
23
16
DSRA
39
-
I
Data Set Ready (active LOW). These inputs are associated with individual UART
channels, A through B. A logic 0 on this pin indicates the modem or data set is
powered-on and is ready for data exchange with the UART. This pin has no effect
on the UART’s transmit or receive operation.
DSRB
20
-
DTRA
34
-
O
Data Terminal Ready (active LOW). These outputs are associated with individual
UART channels, A through B. A logic 0 on this pin indicates that the SC16C652B is
powered-on and ready. This pin can be controlled via the modem control register.
Writing a logic 1 to MCR[0] will set the DTR output to logic 0, enabling the modem.
This pin will be a logic 1 after writing a logic 0 to MCR[0], or after a reset. This pin
has no effect on the UART’s transmit or receive operation.
DTRB
35
-
D0
44
27
I/O
Data bus (bi-directional). These pins are the 8-bit, 3-state data bus for
transferring information to or from the controlling CPU. D0 is the least signicant bit
and the rst data bit in a transmit or receive serial data stream.
D1
45
28
D2
46
29
D3
47
30
D4
48
31
D5
1
32
D6
2
1
D7
3
2
GND
17
13
I
Signal and power ground.
INTA
30
21
O
Interrupt A, B (3-state). This function is associated with individual channel
interrupts, INTA, INTB. INTA, INTB are enabled when MCR bit 3 is set to a logic 1,
interrupts are enabled in the Interrupt Enable Register (IER), and is active when an
interrupt condition exists. Interrupt conditions include: receiver errors, available
receiver buffer data, transmit buffer empty, or when a modem status ag is
detected.
INTB
29
20
IOR
19
14
I
Read strobe (active LOW strobe). A logic 0 transition on this pin will load the
contents of an internal register dened by address bits A0 to A2 onto the
SC16C652B data bus (D0 to D7) for access by external CPU.
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