參數(shù)資料
型號(hào): SC16C650AIA44
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Universal Asynchronous Receiver/Transmitter (UART) with 32-byte FIFO and infrared (IrDA) encoder/decoder
中文描述: 1 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PQCC44
封裝: PLASTIC, MS-018, SOT-187-2, LCC-44
文件頁數(shù): 24/50頁
文件大?。?/td> 642K
代理商: SC16C650AIA44
Philips Semiconductors
SC16C650A
UART with 32-byte FIFO and IrDA encoder/decoder
Product data
Rev. 04 — 20 June 2003
24 of 50
9397 750 11622
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.6 Modem Control Register (MCR)
This register controls the interface with the modem or a peripheral device.
Table 16:
LCR[5]
X
0
0
1
1
LCR[5] parity selection
LCR[4]
X
0
1
0
1
LCR[3]
0
1
1
1
1
Parity selection
no parity
ODD parity
EVEN parity
force parity ‘1’
forced parity ‘0’
Table 17:
LCR[2]
0
1
1
LCR[2] stop bit length
Word length
5, 6, 7, 8
5
6, 7, 8
Stop bit length (bit times)
1
1-
1
2
2
Table 18:
LCR[1]
0
0
1
1
LCR[1-0] word length
LCR[0]
0
1
0
1
Word length
5
6
7
8
Table 19:
Bit
7
Modem Control Register bits description
Symbol
Description
MCR[7]
Clock select.
Logic 0 = Divide-by-1. The input clock (crystal or external) is
divided by 16 and then presented to the Programmable Baud Rate
Generator (BGR) without further modification, i.e., divide-by-1
(normal default condition).
Logic 1 = Divide-by-4. The divide-by-1 clock described in MCR[7]
equals a logic 0, is further divided by four (see also
Section 6.7
“Programmable baud rate generator”
).
MCR[6]
IR enable.
Logic 0 = Enable the standard modem receive and transmit
input/output interface (normal default condition).
Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs.
While in this mode, the TX/RX output/inputs are routed to the
infrared encoder/decoder. The data input and output levels will
conform to the IrDA infrared interface requirement. As such, while
in this mode, the infrared TX output will be a logic 0 during idle data
conditions.
6
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