參數(shù)資料
型號(hào): SC16C650AIA44
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Universal Asynchronous Receiver/Transmitter (UART) with 32-byte FIFO and infrared (IrDA) encoder/decoder
中文描述: 1 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PQCC44
封裝: PLASTIC, MS-018, SOT-187-2, LCC-44
文件頁數(shù): 21/50頁
文件大?。?/td> 642K
代理商: SC16C650AIA44
Philips Semiconductors
SC16C650A
UART with 32-byte FIFO and IrDA encoder/decoder
Product data
Rev. 04 — 20 June 2003
21 of 50
9397 750 11622
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Transmit operation in mode ‘1’:
When the SC16C650A is in FIFO
mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a
logic 1 when the transmit FIFO is completely full. It will be a logic 0 when
the trigger level has been reached.
Receive operation in mode ‘1’:
When the SC16C650A is in FIFO
mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been
reached, or a Receive Time-Out has occurred, the RXRDY pin will go to
a logic 0. Once activated, it will go to a logic 1 after there are no more
characters in the FIFO.
XMIT FIFO reset.
Logic 0 = No FIFO transmit reset (normal default condition).
Logic 1 = Clears the contents of the transmit FIFO and resets the
FIFO counter logic (the transmit shift register is not cleared or
altered). This bit will return to a logic 0 after clearing the FIFO.
RCVR FIFO reset.
Logic 0 = No FIFO receive reset (normal default condition).
Logic 1 = Clears the contents of the receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
FIFO enable.
Logic 0 = Disable the transmit and receive FIFO (normal default
condition).
Logic 1 = Enable the transmit and receive FIFO.
This bit must be a
‘1’ when other FCR bits are written to, or they will not be
programmed.
2
FCR[2]
1
FCR[1]
0
FCR[0]
Table 11:
FCR[7]
0
0
1
1
RCVR trigger levels
FCR[6]
0
1
0
1
RX FIFO trigger level (bytes)
8
16
24
28
Table 12:
FCR[5]
0
0
1
1
TX FIFO trigger levels
FCR[4]
0
1
0
1
TX FIFO trigger level (bytes)
16
8
24
30
Table 10:
Bit
FIFO Control Register bits description
…continued
Symbol
Description
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