參數(shù)資料
型號(hào): SC16C550B
廠商: NXP Semiconductors N.V.
英文描述: 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
中文描述: 5伏,3.3伏和2.5伏的UART具有16字節(jié)的FIFO
文件頁數(shù): 21/47頁
文件大?。?/td> 229K
代理商: SC16C550B
Philips Semiconductors
SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
Product data
Rev. 02 — 14 December 2004
21 of 47
9397 750 14446
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO
trigger levels, and select the DMA mode.
7.3.1
DMA mode
Mode 0 (FCR bit 3 = ‘0’):
Set and enable the interrupt for each single transmit or
receive operation, and is similar to the 16C450 mode. Transmit Ready (TXRDY) will
go to a logic 0 whenever an empty transmit space is available in the Transmit Holding
Register (THR). Receive Ready (RXRDY) will go to a logic 0 whenever the Receive
Holding Register (RHR) is loaded with a character.
Mode 1 (FCR bit 3 = ‘1’):
Set and enable the interrupt in a block mode operation.
The transmit interrupt is set when the transmit FIFO has at least one empty location.
The receive interrupt is set when the receive FIFO fills to the programmed trigger
level. However, the FIFO continues to fill regardless of the programmed level until the
FIFO is full. RXRDY remains a logic 0 as long as the FIFO fill level is above the
programmed trigger level.
7.3.2
FIFO mode
Table 11:
Bit
7-6
FIFO Control Register bits description
Symbol
Description
FCR[7]
(MSB),
FCR[6]
(LSB)
equals the programmed trigger level. However, the FIFO will continue to
be loaded until it is full. Refer to
Table 12
.
FCR[5]
(MSB),
FCR[4]
(LSB)
FCR[3]
DMA mode select.
Logic 0 = Set DMA mode ‘0’ (normal default condition).
Logic 1 = Set DMA mode ‘1’
Transmit operation in mode ‘0’:
When the SC16C550B is in the
16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode
(FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are
no characters in the transmit FIFO or transmit holding register, the
TXRDY pin will be a logic 0. Once active, the TXRDY pin will go to a
logic 1 after the first character is loaded into the transmit holding
register.
Receive operation in mode ‘0’:
When the SC16C550B is in 16C450
mode, or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and
there is at least one character in the receive FIFO, the RXRDY pin will
be a logic 0. Once active, the RXRDY pin will go to a logic 1 when there
are no more characters in the receiver.
RCVR trigger. These bits are used to set the trigger level for the receive
FIFO interrupt.
An interrupt is generated when the number of characters in the FIFO
5-4
Not used; set to 00.
3
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