參數(shù)資料
型號(hào): SC16C550B
廠商: NXP Semiconductors N.V.
英文描述: 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
中文描述: 5伏,3.3伏和2.5伏的UART具有16字節(jié)的FIFO
文件頁(yè)數(shù): 20/47頁(yè)
文件大?。?/td> 229K
代理商: SC16C550B
Philips Semiconductors
SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
Product data
Rev. 02 — 14 December 2004
20 of 47
9397 750 14446
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
7.2.1
IER versus Receive FIFO interrupt mode operation
When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1)
are enabled, the receive interrupts and register status will reflect the following:
The receive data available interrupts are issued to the external CPU when the
FIFO has reached the programmed trigger level. It will be cleared when the FIFO
drops below the programmed trigger level.
FIFO status will also be reflected in the user accessible ISR register when the
FIFO trigger level is reached. Both the ISR register status bit and the interrupt will
be cleared when the FIFO drops below the trigger level.
The data ready bit (LSR[0]) is set as soon as a character is transferred from the
shift register to the receive FIFO. It is reset when the FIFO is empty.
7.2.2
IER versus Receive/Transmit FIFO polled mode operation
When FCR[0] = logic 1, resetting IER[0:3] enables the SC16C550B in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the
LSR, either or both can be used in the polled mode by selecting respective transmit or
receive control bit(s).
LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.
LSR[1:4] will provide the type of errors encountered, if any.
LSR[5] will indicate when the transmit FIFO is empty.
LSR[6] will indicate when both the transmit FIFO and transmit shift register are
empty.
LSR[7] will indicate any FIFO data errors.
相關(guān)PDF資料
PDF描述
SC16C550BIN40 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
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