參數(shù)資料
型號: SC16C550B
廠商: NXP Semiconductors N.V.
英文描述: 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
中文描述: 5伏,3.3伏和2.5伏的UART具有16字節(jié)的FIFO
文件頁數(shù): 10/47頁
文件大小: 229K
代理商: SC16C550B
Philips Semiconductors
SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
Product data
Rev. 02 — 14 December 2004
10 of 47
9397 750 14446
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
6.1 Internal registers
The SC16C550B provides 12 internal registers for monitoring and control. These
registers are shown in
Table 3
. These registers function as data holding registers
(THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register
(FCR), line status and control registers (LCR/LSR), modem status and control
registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM),
and a user accessible scratchpad register (SPR). Register functions are more fully
described in the following paragraphs.
[1]
[2]
These registers are accessible only when LCR[7] is a logic 0.
These registers are accessible only when LCR[7] is a logic 1.
6.2 FIFO operation
The 16-byte transmit and receive data FIFOs are enabled by the FIFO Control
Register bit-0 (FCR[0]). With 16C550 devices, the user can set the receive trigger
level, but not the transmit trigger level. The receiver FIFO section includes a time-out
function to ensure data is delivered to the external CPU. An interrupt is generated
whenever the Receive Holding Register (RHR) has not been read following the
loading of a character or the receive trigger level has not been reached.
Table 3:
A2
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR/LSR, SPR)
[1]
0
0
0
Receive Holding Register
0
0
1
Interrupt Enable Register
0
1
0
Interrupt Status Register
0
1
1
Line Control Register
1
0
0
Modem Control Register
1
0
1
Line Status Register
1
1
0
Modem Status Register
1
1
1
Scratchpad Register
Baud rate register set (DLL/DLM)
[2]
0
0
0
LSB of Divisor Latch
0
0
1
MSB of Divisor Latch
Internal registers decoding
A0
READ mode
A1
WRITE mode
Transmit Holding Register
Interrupt Enable Register
FIFO Control Register
Line Control Register
Modem Control Register
n/a
n/a
Scratchpad Register
LSB of Divisor Latch
MSB of Divisor Latch
Table 4:
Selected trigger level
(characters)
1
4
8
14
Flow control mechanism
INT pin activation
Negate RTS
Assert RTS
1
4
8
14
1
4
8
14
0
0
0
0
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