SC16C2552B_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 12 February 2009
4 of 38
NXP Semiconductors
SC16C2552B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
D0
2
I/O
Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for transferring
information to or from the controlling CPU.
D1
3
I/O
D2
4
I/O
D3
5
I/O
D4
6
I/O
D5
7
I/O
D6
8
I/O
D7
9
I/O
DSRA
41
I
Data Set Ready A, B (active LOW). These inputs are associated with individual UART
channels A through B. A logic 0 on this pin indicates the modem or data set is powered-on
and is ready for data exchange with the UART.
DSRB
29
I
DTRA
37
O
Data Terminal Ready A, B (active LOW). These outputs are associated with individual
UART channels A through B. A logic 0 on this pin indicates that the SC16C2552B is
powered-on and ready. This pin can be controlled via the modem control register. Writing a
logic 1 to MCR[0] will set the DTRn output to logic 0, enabling the modem. This pin will be a
logic 1 after writing a logic 0 to MCR[0], or after a reset.
DTRB
27
O
GND
12, 22
I
Signal and power ground.
INTA
34
O
Interrupt A, B (active HIGH). This function is associated with individual channel interrupts.
Interrupts are enabled in the Interrupt Enable Register (IER). Interrupt conditions include:
receiver errors, available receiver buffer data, transmit buffer empty, or when a modem
status ag is detected.
INTB
17
O
IOR
24
I
Read strobe (active LOW). A logic 0 transition on this pin will load the contents of an
internal register dened by address bits A[2:0] onto the SC16C2552B data bus (D[7:0]) for
access by external CPU.
IOW20
I
Write strobe (active LOW). A logic 0 transition on this pin will transfer the contents of the
data bus (D[7:0]) from the external CPU to an internal register that is dened by address bits
A[2:0].
MFA35
O
Multi-function A, B. This function is associated with an individual channel function, A or B.
User programmable bits 2:1 of the Alternate Function Register (AFR) selects a signal
function or output on these pins. OP2 (interrupt enable), BAUDOUT, and RXRDY are signal
functions that may be selected by the AFR. These signal functions are described as follows:
OP2. When OP2 is selected, the MFn pin is a logic 0 when MCR[3] is set to a logic 1.
A logic 1 is the default signal condition that is available following a master reset or
power-up.
BAUDOUT. When BAUDOUT function is selected, the 16
× baud rate clock output is
available at this pin.
RXRDY. RXRDY is primarily intended for monitoring DMA mode 1 transfers for the receive
data FIFOs. A logic 0 indicates there is receive data to read/unload, i.e., receive ready
status with one or more RX characters available in the FIFO/RHR. This pin is a logic 1
when the FIFO/RHR is empty or when the programmed trigger level has not been
reached. This signal can also be used for single mode transfers (DMA mode 0).
MFB
19
O
RESET
21
I
Reset (active HIGH). A logic 1 on this pin will reset the internal registers and all the outputs.
The UART transmitter output and the receiver input will be disabled during reset time. See
RIA
43
I
Ring Indicator A, B (active LOW). These inputs are associated with individual UART
channels A through B. A logic 0 on this pin indicates the modem has received a ringing
signal from the telephone line. A logic 1 transition on this input pin will generate an interrupt
if modem status interrupt is enabled.
RIB
31
I
Table 2.
Pin description …continued
Symbol
Pin
Type
Description