參數(shù)資料
型號: SC16C2552BIA44,518
廠商: NXP Semiconductors
文件頁數(shù): 2/37頁
文件大?。?/td> 0K
描述: IC UART DUAL SOT187-2
標準包裝: 500
特點: 2 通道
通道數(shù): 2,DUART
FIFO's: 16 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調制解調器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應商設備封裝: 44-PLCC
包裝: 帶卷 (TR)
其它名稱: 935274408518
SC16C2552BIA44-T
SC16C2552BIA44-T-ND
SC16C2552B_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 12 February 2009
10 of 38
NXP Semiconductors
SC16C2552B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
made available at the user data interface D0 to D7. The user optionally compares the
received data to the initial transmitted data for verifying error-free operation of the UART
TX/RX circuits.
In this mode, the receiver and transmitter interrupts are fully operational. The Modem
Control Interrupts are also operational. However, the interrupts can only be read using
lower four bits of the Modem Status Register (MSR[3:0]) instead of the four Modem Status
Register bits 7:4. The interrupts are still controlled by the IER.
Fig 4.
Internal Loopback mode diagram
CTSA, CTSB
TRANSMIT
FIFO
REGISTERS
TXA, TXB
RECEIVE
SHIFT
REGISTER
RECEIVE
FIFO
REGISTERS
RXA, RXB
INTERCONNECT
B
US
LINES
AND
CONTR
OL
SIGNALS
SC16C2552B
TRANSMIT
SHIFT
REGISTER
002aaa489
DATA BUS
AND
CONTROL
LOGIC
REGISTER
SELECT
LOGIC
INTERRUPT
CONTROL
LOGIC
D0 to D7
IOR
IOW
RESET
INTA, INTB
TXRDYA, TXRDYB
RXRDYA, RXRDYB
CLOCK AND
BAUD RATE
GENERATOR
MODEM
CONTROL
LOGIC
RTSA, RTSB
DSRA, DSRB
DTRA, DTRB
RIA, RIB
(OP1A, OP1B)
CDA, CDB
(OP2A, OP2B)
MCR[4] = 1
XTAL2
XTAL1
A0 to A2
CS
CHSEL
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