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| 型號(hào)： | SC16C2550IB48,157 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 44/46頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DUART SOT313-2 |
| 標(biāo)準(zhǔn)包裝： | 1,250 |
| 特點(diǎn)： | 2 通道 |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 16 字節(jié) |
| 電源電壓： | 2.5V，3.3V，5V |
| 帶自動(dòng)流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動(dòng)位檢測(cè)功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 管件 |
| 其它名稱： | 935270020157 SC16C2550IB48 SC16C2550IB48-ND |
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Philips Semiconductors
SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
Product data
Rev. 03 — 19 June 2003
7 of 46
9397 750 11621
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
INTA,
INTB
30, 29 33, 32
30, 29
O
Interrupt A, B (3-State). This function is associated with individual channel
interrupts, INTA, INTB. INTA, INTB are enabled when MCR bit 3 is set to a
logic 1, interrupts are enabled in the interrupt enable register (IER), and is
active when an interrupt condition exists. Interrupt conditions include:
receiver errors, available receiver buffer data, transmit buffer empty, or
when a modem status ag is detected.
IOR
21
24
19
I
Read strobe (Active-LOW strobe). A logic 0 transition on this pin will load
the contents of an internal register dened by address bits A0-A2 onto the
SC16C2550 data bus (D0-D7) for access by external CPU.
IOW18
20
15
I
Write strobe (Active-LOW strobe). A logic 0 transition on this pin will
transfer the contents of the data bus (D0-D7) from the external CPU to an
internal register that is dened by address bits A0-A2.
OP2A,
OP2B
31, 13 35, 15
32, 9
O
Output 2 (user-dened). This function is associated with individual
channels, A through B. The state at these pin(s) are dened by the user
and through MCR register bit 3. INTA, INTB are set to the active mode and
OP2 to logic 0 when MCR[3] is set to a logic 1. INTA, INTB are set to the
3-State mode and OP2 to a logic 1 when MCR[3] is set to a logic 0. See
bit 3, Modem Control Register (MCR[3]). Since these bits control both the
INTA, INTB operation and OP2 outputs, only one function should be used
at one time, INT or OP2.
RESET
35
39
36
I
Reset (Active-HIGH). A logic 1 on this pin will reset the internal registers
and all the outputs. The UART transmitter output and the receiver input will
be disabled during reset time. (See Section 7.11 “SC16C2550 external
reset condition” for initialization details.)
RXRDYA,
RXRDYB
-
34, 23
31, 18
O
Receive Ready A, B (Active-LOW). This function is associated with
PLCC44 and LQFP48 packages only. This function provides the
RX FIFO/RHR status for individual receive channels (A-B). RXRDYn is
primarily intended for monitoring DMA mode 1 transfers for the receive data
FIFOs. A logic 0 indicates there is a receive data to read/upload, i.e.,
receive ready status with one or more RX characters available in the
FIFO/RHR. This pin is a logic 1 when the FIFO/RHR is empty or when the
programmed trigger level has not been reached. This signal can also be
used for single mode transfers (DMA mode 0).
TXRDYA,
TXRDYB
-
1, 12
43, 6
O
Transmit Ready A, B (Active-LOW). This function is associated with
PLCC44 and LQFP48 packages only. These outputs provide the
TX FIFO/THR status for individual transmit channels (A-B). TXRDYn is
primarily intended for monitoring DMA mode 1 transfers for the transmit
data FIFOs. An individual channel’s TXRDYA, TXRDYB buffer ready status
is indicated by logic 0, i.e., at lease one location is empty and available in
the FIFO or THR. This pin goes to a logic 1 (DMA mode 1) when there are
no more empty locations in the FIFO or THR. This signal can also be used
for single mode transfers (DMA mode 0).
VCC
40
44
42
I
Power supply input.
XTAL1
16
18
13
I
Crystal or external clock input. Functions as a crystal input or as an
external clock input. A crystal can be connected between this pin and
XTAL2 to form an internal oscillator circuit. This conguration requires an
external 1 M
resistor between the XTAL1 and XTAL2 pins. Alternatively,
an external clock can be connected to this pin to provide custom data rates.
Table 2:
Pin description…continued
Symbol
Pin
Type Description
DIP40 PLCC44 LQFP48
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SC16C2550IA44,518 | IC DUART SOT187-2 |
| SC16C2550IA44,512 | IC DUART SOT187-2 |
| VI-B7N-IX-F1 | CONVERTER MOD DC/DC 18.5V 75W |
| SC16C2550BIN40,112 | IC UART DUAL W/FIFO 40-DIP |
| VI-B7N-IW-F4 | CONVERTER MOD DC/DC 18.5V 100W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SC16C2550IN40 | 制造商:PHILIP 功能描述: |
| SC16C2550IN40,112 | 功能描述:IC UART DUAL W/FIFO 40-DIP RoHS:是 類別:集成電路 (IC) >> 接口 - UART（通用異步接收器/發(fā)送器） 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 特點(diǎn):* 通道數(shù):2，DUART FIFO's:16 字節(jié) 規(guī)程:RS232，RS485 電源電壓:2.25 V ~ 5.5 V 帶并行端口:- 帶自動(dòng)流量控制功能:是 帶IrDA 編碼器/解碼器:是 帶故障啟動(dòng)位檢測(cè)功能:是 帶調(diào)制解調(diào)器控制功能:是 帶CMOS:是 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:托盤 其它名稱:XR16L2551IM-F-ND |
| SC16C2552 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual UART with 16-byte transmit and receive FIFOs |
| SC16C2552B | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs |
| SC16C2552BIA44 | 功能描述:UART 接口集成電路 16CB 2.5V-5V 2CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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