- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄11813 > SC16C2550IB48,157 (NXP Semiconductors)IC DUART SOT313-2 PDF資料下載
參數(shù)資料
| 型號(hào)： | SC16C2550IB48,157 |
| 廠商： | NXP Semiconductors |
| 文件頁(yè)數(shù)： | 15/46頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DUART SOT313-2 |
| 標(biāo)準(zhǔn)包裝： | 1,250 |
| 特點(diǎn)： | 2 通道 |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 16 字節(jié) |
| 電源電壓： | 2.5V，3.3V，5V |
| 帶自動(dòng)流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動(dòng)位檢測(cè)功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 管件 |
| 其它名稱： | 935270020157 SC16C2550IB48 SC16C2550IB48-ND |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)當(dāng)前第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)
Philips Semiconductors
SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
Product data
Rev. 03 — 19 June 2003
22 of 46
9397 750 11621
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by
writing the appropriate bits in this register.
Table 12:
Interrupt Status Register bits description
Bit
Symbol
Description
7-6
ISR[7-6]
FIFOs enabled. These bits are set to a logic 0 when the FIFOs are
not being used in the 16C450 mode. They are set to a logic 1
when the FIFOs are enabled in the SC16C2550 mode.
Logic 0 or cleared = default condition.
5-4
ISR[5-4]
INT priority bits 4-3. These bits are enabled when EFR[4] is set to
a logic 1. ISR[4] indicates that matching Xoff character(s) have
been detected. ISR[5] indicates that CTS, RTS have been
generated. Note that once set to a logic 1, the ISR[4] bit will stay a
logic 1 until Xon character(s) are received.
Logic 0 or cleared = default condition.
3-1
ISR[3-1]
INT priority bits 2-0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3 (see Table 11).
Logic 0 or cleared = default condition.
0
ISR[0]
INT status.
Logic 0 = An interrupt is pending and the ISR contents may be
used as a pointer to the appropriate interrupt service routine.
Logic 1 = No interrupt pending (normal default condition).
Table 13:
Line Control Register bits description
Bit
Symbol
Description
7
LCR[7]
Divisor latch enable. The internal baud rate counter latch and
Enhance Feature mode enable.
Logic 0 = Divisor latch disabled (normal default condition).
Logic 1 = Divisor latch enabled.
6
LCR[6]
Set break. When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to a logic 0
state). This condition exists until disabled by setting LCR[6] to a
logic 0.
Logic 0 = no TX break condition (normal default condition)
Logic 1 = forces the transmitter output (TX) to a logic 0 for
alerting the remote receiver to a line break condition.
5-3
LCR[5-3]
Programs the parity conditions (see Table 14).
2
LCR[2]
Stop bits. The length of stop bit is specied by this bit in
conjunction with the programmed word length (see Table 15).
Logic 0 or cleared = default condition.
1-0
LCR[1-0]
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see Table 16).
Logic 0 or cleared = default condition.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SC16C2550IA44,518 | IC DUART SOT187-2 |
| SC16C2550IA44,512 | IC DUART SOT187-2 |
| VI-B7N-IX-F1 | CONVERTER MOD DC/DC 18.5V 75W |
| SC16C2550BIN40,112 | IC UART DUAL W/FIFO 40-DIP |
| VI-B7N-IW-F4 | CONVERTER MOD DC/DC 18.5V 100W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SC16C2550IN40 | 制造商:PHILIP 功能描述: |
| SC16C2550IN40,112 | 功能描述:IC UART DUAL W/FIFO 40-DIP RoHS:是 類別:集成電路 (IC) >> 接口 - UART（通用異步接收器/發(fā)送器） 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 特點(diǎn):* 通道數(shù):2，DUART FIFO's:16 字節(jié) 規(guī)程:RS232，RS485 電源電壓:2.25 V ~ 5.5 V 帶并行端口:- 帶自動(dòng)流量控制功能:是 帶IrDA 編碼器/解碼器:是 帶故障啟動(dòng)位檢測(cè)功能:是 帶調(diào)制解調(diào)器控制功能:是 帶CMOS:是 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:托盤 其它名稱:XR16L2551IM-F-ND |
| SC16C2552 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual UART with 16-byte transmit and receive FIFOs |
| SC16C2552B | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs |
| SC16C2552BIA44 | 功能描述:UART 接口集成電路 16CB 2.5V-5V 2CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。