參數(shù)資料
型號(hào): SC16C2550IB48,157
廠商: NXP Semiconductors
文件頁(yè)數(shù): 19/46頁(yè)
文件大?。?/td> 0K
描述: IC DUART SOT313-2
標(biāo)準(zhǔn)包裝: 1,250
特點(diǎn): 2 通道
通道數(shù): 2,DUART
FIFO's: 16 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 管件
其它名稱: 935270020157
SC16C2550IB48
SC16C2550IB48-ND
Philips Semiconductors
SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
Product data
Rev. 03 — 19 June 2003
26 of 46
9397 750 11621
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.8 Modem Status Register (MSR)
This register provides the current state of the control interface signals from the
modem, or other peripheral device to which the SC16C2550 is connected. Four bits
of this register are used to indicate the changed information. These bits are set to a
logic 1 whenever a control input from the modem changes state. These bits are set to
a logic 0 whenever the CPU reads this register.
1
LSR[1]
Overrun error.
Logic 0 = No overrun error (normal default condition).
Logic1=Overrun error. A data overrun error occurred in the
receive shift register. This happens when additional data arrives
while the FIFO is full. In this case, the previous data in the shift
register is overwritten. Note that under this condition, the data
byte in the receive shift register is not transferred into the FIFO,
therefore the data in the FIFO is not corrupted by the error.
0
LSR[0]
Receive data ready.
Logic 0 = No data in receive holding register or FIFO (normal
default condition).
Logic 1 = Data has been received and is saved in the receive
holding register or FIFO.
Table 18:
Line Status Register bits description…continued
Bit
Symbol
Description
Table 19:
Modem Status Register bits description
Bit
Symbol
Description
7
MSR[7]
CD. During normal operation, this bit is the complement of the CD
input. Reading this bit in the loop-back mode produces the state of
MCR[3] (OP2).
6
MSR[6]
RI. During normal operation, this bit is the complement of the RI
input. Reading this bit in the loop-back mode produces the state of
MCR[2] (OP1).
5
MSR[5]
DSR. During normal operation, this bit is the complement of the
DSR input. During the loop-back mode, this bit is equivalent to
MCR[0] (DTR).
4
MSR[4]
CTS. During normal operation, this bit is the complement of the
CTS input. During the loop-back mode, this bit is equivalent to
MCR[1] (RTS).
3
MSR[3]
CD [1]
Logic 0 = No CD change (normal default condition).
Logic 1 = The CD input to the SC16C2550 has changed state
since the last time it was read. A modem Status Interrupt will be
generated.
2
MSR[2]
RI [1]
Logic 0 = No RI change (normal default condition).
Logic 1 = The RI input to the SC16C2550 has changed from a
logic 0 to a logic 1. A modem Status Interrupt will be generated.
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