參數(shù)資料
型號： SAK-C164SV-2RF
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP64
封裝： PLASTIC, TQFP-64
文件頁數(shù)： 53/65頁
文件大?。?/td> 932K
代理商： SAK-C164SV-2RF
C164SV
Data Sheet
53
V1.0, 2003-04
Preliminary
Memory Cycle Variables
The timing tables below use three variables which are derived from the BUSCONx
registers and represent the special characteristics of the programmed memory cycle.
The following table describes, how these variables are to be computed.
Note: Please respect the maximum operating frequency of the respective derivative.
AC Characteristics
Table 15
Memory Cycle Variables
Description
Symbol
Values
ALE Extension
tA
TCL
× <ALECTL>
Memory Cycle Time Waitstates
tC
2TCL
× (15 - <MCTC>)
Memory Tristate Time
tF
2TCL
× (1 - <MTTC>)
Multiplexed Bus
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2
tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 25 MHz
Variable CPU Clock
1 / 2TCL = 1 to 25 MHz
Unit
min.
max.
min.
max.
ALE high time
t5
CC
10 +
tA
–TCL - 10
+
tA
–ns
Address setup to ALE
t6
CC
4 +
tA
–TCL - 16
+
tA
–ns
Address hold after ALE
t7
CC
10 +
tA
–TCL - 10
+
tA
–ns
ALE falling edge to RD,
WR (with RW-delay)
t8
CC
10 +
tA
–TCL - 10
+
tA
–ns
ALE falling edge to RD,
WR (no RW-delay)
t9
CC
-10 +
tA –
-10 +
tA
–ns
Address float after RD,
WR (with RW-delay)
t10 CC –
6
–6ns
Address float after RD,
WR (no RW-delay)
t11 CC –
26
–
TCL + 6
ns
RD, WR low time
(with RW-delay)
t12 CC 30 + tC
–
2TCL - 10
+
tC
–ns
相關(guān)PDF資料
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