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| 型號： | SAH-XC2336A-72F80L |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP64 |
| 封裝： | 0.50 MM PITCH, GREEN, PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 35/106頁 |
| 文件大?。?/td> | 1607K |
| 代理商： | SAH-XC2336A-72F80L |
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XC2336A
XC2000 Family / Base Line
Functional Description
Data Sheet
34
V2.1, 2011-07
3.5
Interrupt System
The architecture of the XC233xA supports several mechanisms for fast and flexible
response to service requests; these can be generated from various sources internal or
external to the microcontroller. Any of these interrupt requests can be programmed to be
serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).
Where in a standard interrupt service the current program execution is suspended and
a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the
current CPU activity to perform a PEC service. A PEC service implies a single byte or
word data transfer between any two memory locations with an additional increment of
either the PEC source pointer, the destination pointer, or both. An individual PEC
transfer counter is implicitly decremented for each PEC service except when performing
in the continuous transfer mode. When this counter reaches zero, a standard interrupt is
performed to the corresponding source-related vector location. PEC services are
particularly well suited to supporting the transmission or reception of blocks of data. The
XC233xA has eight PEC channels, each whith fast interrupt-driven data transfer
capabilities.
With a minimum interrupt response time of 7/11
1) CPU clocks, the XC233xA can react
quickly to the occurrence of non-deterministic events.
Interrupt Nodes and Source Selection
The interrupt system provides 96 physical nodes with separate control register
containing an interrupt request flag, an interrupt enable flag and an interrupt priority bit
field. Most interrupt sources are assigned to a dedicated node. A particular subset of
interrupt sources shares a set of nodes. The source selection can be programmed using
the interrupt source selection (ISSR) registers.
External Request Unit (ERU)
A dedicated External Request Unit (ERU) is provided to route and preprocess selected
on-chip peripheral and external interrupt requests. The ERU features 4 programmable
input channels with event trigger logic (ETL) a routing matrix and 4 output gating units
(OGU). The ETL features rising edge, falling edge, or both edges event detection. The
OGU combines the detected interrupt events and provides filtering capabilities
depending on a programmable pattern match or miss.
Trap Processing
The XC233xA provides efficient mechanisms to identify and process exceptions or error
conditions that arise during run-time, the so-called ‘Hardware Traps’. A hardware trap
causes an immediate system reaction similar to a standard interrupt service (branching
1) Depending if the jump cache is used or not.
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| SAH-XC2336B-40F80L AA | 功能描述:16位微控制器 - MCU 16 BIT FLASH C11 BCS RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時鐘頻率:24 MHz 程序存儲器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT |
| SAH-XC2361A-56F80L34 AA | 制造商:Infineon Technologies AG 功能描述:INFSAHXC2361A56F80L34AA SP000473748_MCU_ |
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