參數(shù)資料
型號(hào): SAH-XC2336A-72F80L
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP64
封裝: 0.50 MM PITCH, GREEN, PLASTIC, LQFP-64
文件頁數(shù): 14/106頁
文件大?。?/td> 1607K
代理商: SAH-XC2336A-72F80L
XC2336A
XC2000 Family / Base Line
General Device Information
Data Sheet
15
V2.1, 2011-07
Key to Pin Definitions
Ctrl.: The output signal for a port pin is selected by bit field PC in the associated
register Px_IOCRy. Output O0 is selected by setting the respective bit field PC to
1x00
B, output O1 is selected by 1x01B, etc.
Output signal OH is controlled by hardware.
Type: Indicates the pad type and its power supply domain (A, B, M, 1).
– St: Standard pad
– Sp: Special pad e.g. XTALx
– DP: Double pad - can be used as standard or high speed pad
– In: Input only pad
– PS: Power supply pad
Table 6
Pin Definitions and Functions
Pin
Symbol
Ctrl.
Type Function
3
TESTM
IIn/B
Testmode Enable
Enables factory test modes, must be held HIGH for
normal operation (connect to
V
DDPB).
An internal pull-up device will hold this pin high
when nothing is driving it.
4TRST
IIn/B
Test-System Reset Input
For normal system operation, pin TRST should be
held low. A high level at this pin at the rising edge
of PORST activates the XC233xA’s debug system.
In this case, pin TRST must be driven low once to
reset the debug system.
An internal pull-down device will hold this pin low
when nothing is driving it.
5
P7.0
O0 / I St/B
Bit 0 of Port 7, General Purpose Input/Output
T3OUT
O1
St/B
GPT12E Timer T3 Toggle Latch Output
T6OUT
O2
St/B
GPT12E Timer T6 Toggle Latch Output
TDO_A
OH /
IH
St/B
JTAG Test Data Output / DAP1 Input/Output
If DAP pos. 0 or 2 is selected during start-up, an
internal pull-down device will hold this pin low
when nothing is driving it.
ESR2_1
I
St/B
ESR2 Trigger Input 1
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