參數(shù)資料
型號(hào): SAFC163-L
廠商: SIEMENS AG
元件分類: 圓形連接器
英文描述: Circular Connector; No. of Contacts:37; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:15-35 RoHS Compliant: No
中文描述: 16位CMOS單片機(jī)
文件頁數(shù): 8/68頁
文件大?。?/td> 625K
代理商: SAFC163-L
11Aug98@14:48h Intermediate Version
Semiconductor Group
6
1998-08
C163-L
PORT0
P0L.0-7
P0H.0-7
41 - 48
51 - 58
IO
PORT0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. It
is bit-wise programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-impedance state.
In case of an external bus configuration, PORT0 serves as the address
(A) and address/data (AD) bus in multiplexed bus modes and as the
data (D) bus in demultiplexed bus modes.
Demultiplexed bus modes:
Data Path Width:
8-bit
P0L.0 – P0L.7:
D0 – D7
P0H.0 – P0H.7:
I/O
Multiplexed bus modes:
Data Path Width:
8-bit
P0L.0 – P0L.7:
AD0 – AD7
P0H.0 – P0H.7:
A8 - A15
16-bit
D0 - D7
D8 - D15
16-bit
AD0 - AD7
AD8 - AD15
PORT1
P1L.0-7
P1H.0-7
59 - 66
67, 68,
71 - 76
IO
PORT1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It
is bit-wise programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-impedance state.
PORT1 is used as the 16-bit address bus (A) in demultiplexed bus
modes and also after switching from a demultiplexed bus mode to a
multiplexed bus mode.
RSTIN
79
I
Reset Input with Schmitt-Trigger characteristics. A low level at this pin
for a minimum of 2 CPU clock cycles while the oscillator is running
resets the C163-L. An internal pullup resistor permits power-on reset
using only a capacitor connected to
V
SS
.
Note
:
To let the reset configuration of PORT0 settle and to let the
PLL lock a reset duration of ca. 1 ms is recommended.
RST
OUT
80
O
Internal Reset Indication Output. This pin is set to a low level when the
part is executing either a hardware-, a software- or a watchdog timer
reset. RSTOUT remains low until the EINIT (end of initialization)
instruction is executed.
NMI
81
I
Non-Maskable Interrupt Input. A high to low transition at this pin causes
the CPU to vector to the NMI trap routine. When the PWRDN (power
down) instruction is executed, the NMI pin must be low in order to force
the C163-L to go into power down mode. If NMI is high, when PWRDN
is executed, the part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
Pin Definitions and Functions
(cont’d)
Symbol Pin
Numb.
TQFP
Input
Out-
put
Function
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