參數資料
型號: SAFC163-L
廠商: SIEMENS AG
元件分類: 圓形連接器
英文描述: Circular Connector; No. of Contacts:37; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:15-35 RoHS Compliant: No
中文描述: 16位CMOS單片機
文件頁數: 20/68頁
文件大小: 625K
代理商: SAFC163-L
11Aug98@14:48h Intermediate Version
Semiconductor Group
18
1998-08
C163-L
Parallel Ports
The C163-L provides up to 77 I/O lines which are organized into six input/output ports and one input
port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise)
programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports
which are switched to high impedance state when configured as inputs. The output drivers of three
I/O ports can be configured (pin by pin) for push/pull operation or open-drain operation via control
registers. During the internal reset, all port pins are configured as inputs.
All port lines have programmable alternate input or output functions associated with them. PORT0
and PORT1 may be used as address and data lines when accessing external memory, while Port 4
outputs the additional segment address bits A23/19/17...A16 in systems where segmentation is
enabled to access more than 64 KBytes of memory. Port 6 provides optional bus arbitration signals
(BREQ, HLDA, HOLD) and chip select signals. Port 3 includes alternate functions of timers, serial
interfaces, the optional bus control signal BHE and the system clock output (CLKOUT). Port 5 is
used for timer control signals. All port lines that are not used for these alternate functions may be
used as general purpose I/O lines.
Serial Channels
Serial communication with other microcontrollers, processors, terminals or external peripheral
components is provided by two serial interfaces with different functionality, an Asynchronous/
Synchronous Serial Channel (ASC0) and a Synchronous Serial Port (SSP).
The ASC0
is upward compatible with the serial ports of the Siemens 8-bit microcontroller families
and supports full-duplex asynchronous communication at up to 781 KBaud and half-duplex
synchronous communication at up to 3.125 MBaud @ 25 MHz CPU clock.
A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning.
For transmission, reception and error handling 4 separate interrupt vectors are provided. In
asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and
terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish
address from data bytes has been included (8-bit data plus wake up bit mode).
In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock
which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop back option is
available for testing purposes.
A number of optional hardware error detection capabilities has been included to increase the
reliability of data transfers. A parity bit can automatically be generated on transmission or be
checked on reception. Framing error detection allows to recognize data frames with missing stop
bits. An overrun error will be generated, if the last character received has not been read out of the
receive buffer register at the time the reception of a new character is complete.
The SSP
transmits 1...3 bytes or receives 1 byte after sending 1...3 bytes synchronously to a shift
clock which is generated by the SSP. The SSP can start shifting with the LSB or with the MSB and
allows to select shifting and latching clock edges as well as the clock polarity. Up to two chip select
lines may be activated in order to direct data transfers to one or both of two peripheral devices.
One general interrupt vector is provided for the SSP.
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