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參數(shù)資料
| 型號： | SAF7843HL |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 存儲器 |
| 英文描述： | One chip CD audio device with integrated MP3-WMA decoder |
| 封裝： | SAF7843HL/M295<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.html<1<Always Pb-free,;SAF7849HL/M245<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.h |
| 文件頁數(shù)： | 77/93頁 |
| 文件大?。?/td> | 396K |
| 代理商： | SAF7843HL |
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SAF784X_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2008
77 of 93
NXP Semiconductors
SAF784x
One chip CD audio device with integrated MP3/WMA decoder
7.15.3
EBU interface
The channel decoder contains a digital 1-wire EBU or S/PDIF output interface. It formats
data according to specification IEC 958. The EBU rate can be selected to be 1
×
CD-speed
or 2
×
CD-speed.
For proper operation of the EBU interface, the I
2
S bclk must be internally generated, bit
clock gating must be disabled, and the following relationship between ebuclk, I
2
S bclk and
I
2
S-format must be true:
ebuclk = wclk
×
64
Some fields in the user channel of the EBU stream can be filled by software.
7.16 Reset functionality
The device reset is crucial to the application as it allows the application to be initialized in
the correct state before the key functions of the device can be exercised.
The device reset function depends on the following requirements:
Power supply
System clock
Reset assertion
Normal reset application can be summarized as follows:
The device reset must be asserted asynchronously, that is, dependent only on the power
supply and the reset pin RESET, and de-asserted synchronously, that is, the system clock
OSCIN needs to be available before starting the application.
7.16.1
Power supply requirements
The SAF784x is dependent on two supply voltages of 3.3 V and 1.8 V. It is recommended
that the system solutions ensure the correct supply voltages are applied, during power-up
and available during device initialization via a reset.
7.16.2
System clock
The SAF784x can support two types of external crystal frequencies of 8.4672 MHz and
16.9344 MHz. The digital logic is clocked at lower frequencies to ensure minimum power
consumption during initialization.
Fig 39. VSRC block diagram
001aag350
BUFFER
VARIABLE HOLD
N
M
PLL
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAF7843HL/M295,557 | 功能描述:音頻 DSP IC AUD DECODER RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAF7846HL/M210,557 | 功能描述:音頻 DSP 1 chip CD Audio Dev w/Integrated decoder RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAF7847HL/M201,557 | 功能描述:音頻 DSP 1 chip CD Audio Dev w/Integrated decoder RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAF7849HL/M245,557 | 功能描述:音頻 DSP IC AUD DECODER RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAF7849HL/M295,557 | 功能描述:音頻 DSP IC AUD DECODER RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
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