參數(shù)資料
型號: SAF7118
廠商: NXP Semiconductors N.V.
英文描述: Multistandard video decoder with adaptive comb filter and component video input
中文描述: 多標準視頻解碼器與自適應(yīng)梳狀濾波器和分量視頻輸入
文件頁數(shù): 68/173頁
文件大?。?/td> 950K
代理商: SAF7118
2004 Jul 22
68
Philips Semiconductors
Product speci
fi
cation
Multistandard video decoder with adaptive
comb
fi
lter and component video input
SAF7118
8.7.2
S
IGNALS
ASCLK
AND
ALRCLK
Two binary divided signals ASCLK and ALRCLK are provided for slower serial digital audio signal transmission and for
channel-select. The frequencies of these signals are defined by the following parameters:
SDIV[5:0] 38H[5:0] according to the equation:
f
1
+
)
2
×
ASCLK
LRDIV[5:0] 39H[5:0] according to the equation:
See Table 23 for examples.
Table 23
Programming examples for ASCLK/ALRCLK clock generation
8.7.3
O
THER CONTROL SIGNALS
Further control signals are available to define reference clock edges and vertical references; see Table 24.
Table 24
Control signals for reference clock edges and vertical references
AMXCLK
(MHz)
ASCLK
(kHz)
SDIV
ALRCLK
(kHz)
LRDIV
DECIMAL
HEX
DECIMAL
HEX
12.288
1536
768
1411.2
2822.4
1024
2048
3
7
3
1
3
1
03
07
03
01
03
01
48
16
8
16
32
16
32
10
08
10
10
10
10
11.2896
44.1
8.192
32
SIGNAL
DESCRIPTION
APLL[3AH[3]]
Audio PLL mode
0 = PLL closed
1 = PLL open
Audio Master clock Vertical Reference
0 = internal V
1 = external V
ALRCLK phase
0 = invert ASCLK, ALRCLK edges triggered by falling edge of ASCLK
1 = don’t invert ASCLK, ALRCLK edges triggered by rising edge of ASCLK
ASCLK phase
0 = invert AMXCLK, ASCLK edges triggered by falling edge of AMXCLK
1 = don’t invert AMXCLK, ASCLK edges triggered by rising edge of AMXCLK
AMVR[3AH[2]]
LRPH[3AH[1]]
SCPH[3AH[0]]
f
ASCLK
-SDIV
=
SDIV[5:0]
f
AMXCLK
2f
1
=
f
ALRCLK
f
LRDIV
2
×
--------------------------
=
LRDIV[5:0]
f
2f
ALRCLK
----------------------
=
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SAF7118EH Multistandard video decoder with adaptive comb filter and component video input
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