參數(shù)資料
型號: SAF7118
廠商: NXP Semiconductors N.V.
英文描述: Multistandard video decoder with adaptive comb filter and component video input
中文描述: 多標準視頻解碼器與自適應梳狀濾波器和分量視頻輸入
文件頁數(shù): 164/173頁
文件大小: 950K
代理商: SAF7118
2004 Jul 22
164
Philips Semiconductors
Product speci
fi
cation
Multistandard video decoder with adaptive
comb
fi
lter and component video input
SAF7118
16.5
Scaler and interfaces
Table 144 shows some examples for the scaler
programming with:
prsc = prescale ratio
fisc = fine scale ratio
vsc = vertical scale ratio.
The ratio is defined as:
In the following settings the VBI data slicer is inactive.
To activate the VBI data slicer, VITX[1:0] 86H[7:6] has to
be set to ‘11’. Depending on the VBI data slicer settings,
the sliced VBI data is inserted after the end of the scaled
video lines, if the regions of VBI data slicer and scaler
overlaps.
To compensate the running-in of the vertical scaler, the
vertical input window lengths are extended by
2 to 290 lines, respectively 242 lines for XS, but the scaler
increment calculations are done with 288, respectively
240 lines.
16.5.1
T
RIGGER CONDITION
For trigger condition STRC[1:0] 90H[1:0] not equal to ‘00’.
If the value of (YO + YS) is greater than or equal to 262
(NTSC), respectively 312 (PAL) the output field rate is
reduced to 30 Hz, respectively 25 Hz.
Horizontal and vertical offsets (XO and YO) have to be
used to adjust the displayed video in the display window.
As this adjustment is application dependent, the listed
values are only dummy values.
16.5.2
M
AXIMUM ZOOM FACTOR
The maximum zoom factor is dependent on the back-end
data rate and therefore back-end clock and data format
dependent (8 or 16-bit output). The maximum horizontal
zoom is limited to approximately 3.5, due to internal data
path restrictions.
number of output pixel
--number of input pixel
16.5.3
E
XAMPLES
Table 144
Example of con
fi
gurations
EXAMPLE
NUMBER
SCALER SOURCE AND REFERENCE EVENTS
INPUT
WINDOW
720
×
240 720
×
240 prsc = 1;
OUTPUT
WINDOW
SCALE
RATIOS
1
analog input to 8-bit I port output, with SAV/EAV codes, 8-bit
serial byte stream decoder output at X port; acquisition trigger
at falling edge vertical and rising edge horizontal reference
signal; H and V gates on IGPH and IGPV, IGP0 = VBI sliced
data
fl
ag, IGP1 = FIFO almost full, level
24, IDQ quali
fi
er
logic 1 active
analog input to 16-bit output, without SAV/EAV codes, Yon
I port, C
B
-C
R
on H port and decoder output at X port;
acquisition trigger at falling edge vertical and rising edge
horizontal reference signal; H and V-pulses on IGPH and IGPV,
output FID on IGP0, IGP1
fi
xed to logic 1, IDQ quali
fi
er logic 0
active
X port input 8-bit with SAV/EAV codes, no reference signals on
XRH and XRV, XCLK as gated clock;
fi
eld detection and
acquisition trigger on different events; acquisition triggers at
rising edge vertical and rising edge horizontal; I port output
8-bit with SAV/EAV codes like example number 1
X port and H port for 16-bit Y-C
B
-C
R
4 : 2 : 2 input (if no 16-bit
output selected); XRH and XRV as references;
fi
eld detection
and acquisition trigger at falling edge vertical and rising edge
horizontal; I port output 8-bit with SAV/EAV codes, but Yonly
output
fi
sc = 1;
vsc = 1
2
704
×
288 768
×
288 prsc = 1;
fi
sc = 0.91667;
vsc = 1
3
720
×
240 352
×
288 prsc = 2;
fi
sc = 1.022;
vsc = 0.8333
4
720
×
288 200
×
80
prsc = 2;
fi
sc = 1.8;
vsc = 3.6
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