參數(shù)資料
型號: SAF-C165-LM 3V HA
廠商: Infineon Technologies
文件頁數(shù): 5/77頁
文件大?。?/td> 0K
描述: IC MCU 16BIT ROM/LESS MQFP-100
標準包裝: 1
系列: C16xx
核心處理器: C166
芯體尺寸: 16-位
速度: 20MHz
連通性: EBI/EMI,SPI,UART/USART
外圍設備: POR,PWM,WDT
輸入/輸出數(shù): 77
程序存儲器類型: ROMless
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-BQFP
包裝: 剪切帶 (CT)
其它名稱: SAF-C165-LM3VHACT
SAF-C165-LM3VHACT-ND
SAF-C165-LM3VHAINCT
C165
Data Sheet
9
V2.0, 2000-12
RSTIN
79
81
I/O
Reset Input with Schmitt-Trigger characteristics. A
low level at this pin while the oscillator is running
resets the C165. An internal pullup resistor permits
power-on reset using only a capacitor connected to
VSS. A spike filter suppresses input pulses < 10 ns.
Input pulses >100 ns safely pass the filter. The
minimum duration for a safe recognition should be
100 ns + 2 CPU clock cycles.
In bidirectional reset mode (enabled by setting bit
BDRSTEN in register SYSCON) the RSTIN line is
internally pulled low for the duration of the internal
reset sequence upon any reset (HW, SW, WDT).
See note below this table.
Note: To let the reset configuration of PORT0 settle
a reset duration of ca. 1 ms is recommended.
RST
OUT
80
82
O
Internal Reset Indication Output. This pin is set to a
low level when the part is executing either a
hardware-, a software- or a watchdog timer reset.
RSTOUT remains low until the EINIT (end of
initialization) instruction is executed.
NMI
81
83
I
Non-Maskable Interrupt Input. A high to low
transition at this pin causes the CPU to vector to the
NMI trap routine. When the PWRDN (power down)
instruction is executed, the NMI pin must be low in
order to force the C165 to go into power down mode.
If NMI is high, when PWRDN is executed, the part
will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin Nr
TQFP
Pin Nr
MQFP
Input
Outp.
Function
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