參數(shù)資料
型號(hào): SAF-C165-LM 3V HA
廠商: Infineon Technologies
文件頁數(shù): 3/77頁
文件大?。?/td> 0K
描述: IC MCU 16BIT ROM/LESS MQFP-100
標(biāo)準(zhǔn)包裝: 1
系列: C16xx
核心處理器: C166
芯體尺寸: 16-位
速度: 20MHz
連通性: EBI/EMI,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 77
程序存儲(chǔ)器類型: ROMless
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-BQFP
包裝: 剪切帶 (CT)
其它名稱: SAF-C165-LM3VHACT
SAF-C165-LM3VHACT-ND
SAF-C165-LM3VHAINCT
C165
Data Sheet
7
V2.0, 2000-12
P4
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
23
24
25
26
29
30
31
32
25
26
27
28
31
32
33
34
IO
O
Port 4 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits.
For a pin configured as input, the output driver is put
into high-impedance state. Port 4 can be used to
output the segment address lines:
A16 Least Significant Segment Address Line
A17 Segment Address Line
A18 Segment Address Line
A19 Segment Address Line
A20 Segment Address Line
A21 Segment Address Line
A22 Segment Address Line
A23 Most Significant Segment Address Line
RD
33
35
O
External Memory Read Strobe. RD is activated for
every external instruction or data read access.
WR/
WRL
34
36
O
External Memory Write Strobe. In WR-mode this pin
is activated for every external data write access. In
WRL-mode this pin is activated for low byte data
write accesses on a 16-bit bus, and for every data
write access on an 8-bit bus. See WRCFG in register
SYSCON for mode selection.
READY 35
37
I
Ready Input. When the Ready function is enabled, a
high level at this pin during an external memory
access will force the insertion of memory cycle
waitstates until the pin returns to a low level.
An internal pullup device holds this pin high when
nothing is driving it.
ALE
36
38
O
Address Latch Enable Output. Can be used for
latching the address into external memory or an
address latch in the multiplexed bus modes.
EA
37
39
I
External Access Enable pin. A low level at this pin
during and after Reset forces the C165 to begin
instruction execution out of external memory. A high
level forces execution out of the internal program
memory.
“ROMless” versions must have this pin tied to ‘0’.
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin Nr
TQFP
Pin Nr
MQFP
Input
Outp.
Function
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