參數(shù)資料
型號： SAF-C161S-LM 3V AA
廠商： Infineon Technologies
文件頁數(shù)： 46/75頁
文件大?。?/td> 0K
描述： IC MCU 16BIT ROM/LESS MQFP-80-7
標(biāo)準(zhǔn)包裝： 1
系列： C16xx
核心處理器： C166
芯體尺寸： 16-位
速度： 20MHz
連通性： EBI/EMI，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 63
程序存儲器類型： ROMless
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 80-QFP
包裝： 剪切帶 (CT)
其它名稱： SAF-C161S-LM3VAACT
SAF-C161S-LM3VAACT-ND
SAF-C161S-LM3VAAINCT
C161S
Timing Characteristics
Data Sheet
46
V1.0, 2003-11
The timings listed in the AC Characteristics that refer to TCLs therefore must be
calculated using the minimum TCL that is possible under the respective circumstances.
The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCL is lower than
for one single TCL (see formula and Figure 11).
For a period of N
× TCL the minimum value is computed using the corresponding
deviation D
N:
(N
× TCL)
min = N × TCLNOM - DN, DN [ns] = ±(13.3 + N × 6.3) / fCPU [MHz]
(1)
where N = number of consecutive TCLs and 1
≤ N ≤ 40.
So for a period of 3 TCLs @ 20 MHz (i.e. N = 3): D
3 = (13.3 + 3 × 6.3) / 20 = 1.61 ns,
and (3TCL)
min = 3TCLNOM - 1.61 ns = 73.39 ns (@ fCPU = 20 MHz).
This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
Note: For all periods longer than 40 TCL the N = 40 value can be used (see Figure 11).
Figure 11
Approximated Maximum Accumulated PLL Jitter
MCD04455
N
Max. jitter
D
N
±1
±10
±20
±30
ns
±26.5
110
20
40
This approximated formula is valid for
1
N
40 and 10 MHz
f
CPU
25 MHz.
10 MHz
16 MHz
20 MHz
25 MHz
30
<
–
<
–
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–
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