參數(shù)資料
型號： SAB82526N
廠商： INFINEON TECHNOLOGIES AG
英文描述： Data Communications ICs
中文描述： 數(shù)據(jù)通信集成電路
文件頁數(shù)： 90/126頁
文件大小： 730K
代理商： SAB82526N
Semiconductor Group
90
SAB 82525
SAB 82526
SAF 82525
SAF 82526
TMD … Timer Mode
The operation mode of the internal timer is set.
0 … external mode
The timer is controlled by the CPU and can be started at any time setting the STI bit in
CMDR.
1 … internal mode
The timer is used internally by the HSCX for time-out and retry conditions in auto-mode.
(refer to the description of the TIMR register)
RAC … Receiver Active
Switches the receiver to inoperational state.
0 … HDLC receiver inactive
1 … HDLC receiver active
In extended transparent modes this bit must be reset to enable fully transparent reception!
RTS … Request To Send
Defines the state and control of RTS pin.
0 … The RTS pin is controlled by the HSCX autonomously.
RTS is activated when a frame transmission starts and deactivated after the transmission
operation is completed.
1 … The RTS pin is controlled by the CPU.
If this bit is set, the RTS pin is activated immediately and remains active till this bit is reset
(not valid in bus configuration).
TRS … Timer Resolution
The resolution of the internal timer (factor
k
, see description of TIMR register) is selected
0 …
k
= 32.768
1 …
k
= 512
RxD is disconnected from the mechanical pin and internally connected to TxD of the same
channel. TxD pin remains active.
TLP … Test Loop
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