參數(shù)資料
型號: SAB82526N
廠商: INFINEON TECHNOLOGIES AG
英文描述: Data Communications ICs
中文描述: 數(shù)據(jù)通信集成電路
文件頁數(shù): 49/126頁
文件大?。?/td> 730K
代理商: SAB82526N
Semiconductor Group
49
SAB 82525
SAB 82526
SAF 82525
SAF 82526
5.1 Clock Modes
The HSCX includes an internal Oscillator (OSC) as well as independent Baudrate Generator
(BRG) and Digital Phase Locked Loop (DPLL) circuitry for each serial channel.
The transmit and receive clock can be either generated
– externally, and supplied via the R
×
CLK and/or T
×
CLK pins, or
– internally, by means of the
* OSC and/or BRG, and
* DPLL, recovering the receive (and optionally transmit) clock from the received data
stream if an external crystal is connected to the R
×
CLKA-A
×
CLKA pins.
Totally, there are 8 different clocking modes programmable via the CCR1 register, providing a
wide variety of clock generation and clock pin functions, as shown in
table 5.
Table 5
Overview of Clock Modes
Type
Source
Generation
Mode
Clock
Receive
Clock
R
×
CLK Pins
DPLL
OSC
Externally
Internally
0, 1, 5
2, 3, 6, 7
4
Transmit
Clock
T
×
CLK Pins
R
×
CLK Pins
DPLL
BRG/16
OSC
Externally
Internally
0, 2, 6
1, 5
3, 7
2, 6
4
The transmit clock pins (T
×
CLK) may also output clock or control signal in certain clock modes
if programmed as outputs via the CCR2 register (TIO bit set).
The clocking source for the DPLL’s is always the internal BRG; the scaling factor (divider) of
the BRG can be programmed through CCR2 and BGR registers between 1,2,4,6. . .2048.
The HSCX system clock is always derived from the transmit clock thus eliminating the need
for additional clock sources.
5
The two serial interfaces of the HSCX provide two fully independent communications
channels, supporting layer-1 functions to a high degree by various means of clock generation
and clock recovery.
Serial Interface (Layer-1 Functions)
Clock Mode 0 (External Clocks)
Separate, externally generated receive and transmit clocks are forwarded to the HSCX via
their respective pins.
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SAF82525N Data Communications ICs
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