參數(shù)資料
型號(hào)： SAB82526N
廠商： INFINEON TECHNOLOGIES AG
英文描述： Data Communications ICs
中文描述： 數(shù)據(jù)通信集成電路
文件頁數(shù)： 38/126頁
文件大?。?/td> 730K
代理商： SAB82526N
Semiconductor Group
38
SAB 82525
SAB 82526
SAF 82525
SAF 82526
3.3 Error Handling
Depending on the error type, erroneous frames are handled according
table 1.
Table 1
Error Handling
Frame Type
Error Type
Generated
Response
Generated
Interrupt
Rec. Status
I
CRC error
aborted
unexpec. N(S)
unexpec. N(R)
–
–
S-frame
–
RME
RME
–
PCE
CRC error
abort
–
S
CRC error
aborted
unexpec. N(R)
with I-field
–
–
–
–
–
–
PCE
PCE
–
–
Note:
The station variables (V(S), V(R)) are not changed.
4
CPU Interface
4.1 Register Set
The communication between the CPU and the HSCX is done via a set of directly accessible
8-bit registers. The CPU sets the operating modes, controls function sequences, and gets
status information by writing or reading these registers (Command/Status transfer). Complete
information concerning the register functions is provided in detailed register description. The
most important functions programmable via these registers are:
– setting of operating and clocking modes
– layer-2 functions
– data transfer modes (Interrupt, DMA)
– bus mode
– DPLL mode
– baudrate generator
– test loop
Each of two serial channels of HSCX is controlled via an equal, but totally independent register
file (channel A and channel B).
4.2 Data Transfer Modes
Data transfer between the system memory and the HSCX for both transmit and receive
direction is controlled by either interrupts (Interrupt Mode), or independently from CPU
interaction using the HSCX’s 4-channel DMA interface (DMA Mode).
After RESET, the HSCX operates in Interrupt Mode, where data transfer must be done by the
CPU. The user selects the DMA Mode by setting the DMA bit in the XBCH register. Both
channels can be independently operated in either Interrupt or DMA Mode (e.g. Channel
A-DMA, Channel B-Interrupt).
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