參數(shù)資料
型號(hào)： SAB-C163-LF
廠商： SIEMENS AG
英文描述： 16-bit CMOS Single-Chip Microcontroller
中文描述： 16位CMOS單片機(jī)
文件頁(yè)數(shù)： 38/68頁(yè)
文件大?。?/td> 625K
代理商： SAB-C163-LF
11Aug98@14:48h Intermediate Version
Semiconductor Group
36
1998-08
C163-L
Phase Locked Loop
For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked loop is
enabled and provides the CPU clock (see table above). The PLL multiplies the input frequency by
the factor
F
which is selected via the combination of pins P0.15-13 (i.e. f
CPU
= f
OSC
*
F
). With every
F
’th transition of f
OSC
the PLL circuit synchronizes the CPU clock to the input clock. This
synchronization is done smoothely, i.e. the CPU clock frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of f
CPU
is constantly adjusted so it is locked
to f
OSC
. The slight variation causes a jitter of f
CPU
which also effects the duration of individual TCLs.
The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the
minimum TCL that is possible under the respective circumstances.
The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is constantly
adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator)
the relative deviation for periods of more than one TCL is lower than for one single TCL (see formula
and figure below).
For a period of
N
* TCL the minimum value is computed using the corresponding deviation D
N
:
(
N
* TCL)
min
=
N
* TCL
NOM
- D
N
where
N
= number of consecutive TCLs
D
N
[ns] =
±
(13.3 +
N
*6.3) / f
CPU
[MHz],
and 1
≤
N
≤
40.
So for a period of 3 TCLs @ 25 MHz (i.e.
N
= 3): D
3
= (13.3 +
3
* 6.3) / 25 = 1.288 ns,
and (3TCL)
min
= 3TCL
NOM
- 1.288 ns = 58.7 ns (@ f
CPU
= 25 MHz).
This is especially important for bus cycles using waitstates and e.g. for the operation of timers, serial
interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or
measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is neglectible.
Note:
For all periods longer than 40 TCL the N=40 value can be used (see figure below).
Figure 11
Approximated Maximum Accumulated PLL Jitter
Note:
The PLL only operates within the standard supply voltage range of V
DD
= 4.5 - 5.5 V.
40
20
10
5
1
±
1
±
10
±
20
N
This approximated formula is valid for
1
≤
N
≤
40 and 10MHz
≤
f
CPU
≤
25MHz.
±
26.5
Max.jitter D
N
[ns]
20 MHz
25 MHz
16 MHz
10 MHz
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SAB-C163-LF-CU 制造商:Siemens 功能描述:IC,MICROCONTROLLER,16-BIT,80166 CPU,CMOS,QFP,100PIN,PLASTIC
SABC163LFLU 制造商:INFINEON 功能描述:Step AC
SABC163LFTR 制造商:Infineon Technologies AG 功能描述:MCU 16-bit C166 CISC/RISC ROMLess 5V 100-Pin TQFP T/R
SAB-C163T-16FF 制造商:Rochester Electronics LLC 功能描述:- Bulk
SAB-C164CI-LM 3V CA 功能描述:16位微控制器 - MCU 16BIT ROM/ROMLESS RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時(shí)鐘頻率:24 MHz 程序存儲(chǔ)器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT
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