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參數(shù)資料
| 型號： | SAA7367 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | Bitstream conversion ADC for digital audio systems |
| 中文描述： | 1-CH 18-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | 7.50 MM, PLASTIC, MS-013AD, SOT-137-1, SOP-24 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 113K |
| 代理商： | SAA7367 |
1998 Nov 17
7
Philips Semiconductors
Product specification
Bitstream conversion ADC for
digital audio systems
SAA7367
Table 3
Overall filter characteristics
High-pass filter
An optional I
2
R high-pass filter is provided to remove
unwanted DC components. The operation is selected
when HPEN is HIGH and deselected when LOW. The filter
has the characteristics given in Table 4.
Table 4
High-pass filter characteristics
Serial interface
The serial interface provides 2 formats in master mode
and 4 in slave mode (see Figs 3 and 4). Format 2 is similar
to Philips I
2
S. In all modes, the interface provides up to
18 significant bits of output data per channel. During
standby mode (STDB = LOW), all interface pins are in
their high impedance state. On recovery from standby, the
serial data output SDO is held LOW until valid data is
available from the decimation filter. This time depends on
whether the high-pass filter is selected:
HPEN = 0; T = 1024/f
s
, T = 21.3 ms when f
s
= 48 kHz
HPEN = 1; T = 12288/f
s
, T = 256.0 ms when
f
s
= 48 kHz
Overload detection
The OVLD output is used to indicate when the output data,
in either the left or right channel, is greater than
1 dB
(actual figure
1.023 dB) of the maximum possible digital
swing. When this condition is detected, the OVLD output is
forced HIGH for at least 512f
s
cycles (10.6 ms at
f
s
= 48 kHz). This time-out is reset for each infringement.
ITEM
CONDITION
VALUE (dB)
±
0.1
0.5
60
110
3.52
Pass band ripple
0 to 0.45f
s
0.45 to 0.47f
s
>0.55f
s
0 to 0.42f
s
DC
Stop band
Dynamic range
Gain
ITEM
CONDITION
VALUE
(dB)
Pass band ripple
Pass band gain
Droop
Attenuation at DC
Dynamic range
none
0
0.146
>40
>110
at 0.00042f
s
at 0.00000036f
s
0 to 0.45f
s
Standby mode
The STDB pin activates a power saving mode when the
device function is not required. This pin can also be used
as a chip enable.
On a HIGH-to-LOW transition of the STDB pin, the internal
control circuitry starts a timed power-down sequence. This
takes approximately 32 system clock cycles to complete.
Transitions on STDB that are shorter than 32 clock cycles
may have an indeterminate effect. However, the device
will always recover correctly.
During standby, the following occurs:
The serial interface pins are forced to high impedance
The OVLD output is forced LOW
The analog circuitry is disabled
The nominal external analog node voltages are
maintained by a low-power circuit. This feature ensures
a fast recovery from standby mode.
Note:
since the serial interface pins are high impedance
during standby, these pins could be wire-ORed with other
serial interface ICs.
On a LOW-to-HIGH transition, the device reverts back to
normal operation. This process takes approximately
256 system clock cycles. Before SDO is enabled, the
output data is forced LOW. SDO remains LOW until good
data is available from the decimation filter
(see Section “Serial interface”).
The STDB pin has a Schmitt-trigger input. A simple
power-on-reset function can be effected using an external
capacitor to V
SS
and resistor to V
DD
.
TEST1
This pin is used to select the serial interface format in slave
mode.
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