參數(shù)資料
型號(hào): SAA7367
廠商: NXP SEMICONDUCTORS
元件分類: ADC
英文描述: Bitstream conversion ADC for digital audio systems
中文描述: 1-CH 18-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24
封裝: 7.50 MM, PLASTIC, MS-013AD, SOT-137-1, SOP-24
文件頁數(shù): 4/20頁
文件大?。?/td> 113K
代理商: SAA7367
1998 Nov 17
4
Philips Semiconductors
Product specification
Bitstream conversion ADC for
digital audio systems
SAA7367
PINNING
SYMBOL
PIN
DESCRIPTION
SFOR
1
TTL level input; in normal mode this input selects the serial interface output format; output
format is selected as follows:
SFOR = HIGH selects Format 1
SFOR = LOW selects Format 2 (similar to I
2
S)
schmitt-trigger input; in normal mode, this input is used to select standby mode:
STDB = HIGH selects normal operation
STDB = LOW selects standby mode (low power consumption)
TTL level output; in normal mode this output indicates whether the internal digital signal is
within 1 dB of maximum; if so, the output will go HIGH for 131072 clock cycles (approximately
11 ms); in standby mode this output is forced LOW
CMOS level input; system clock input; nominally clocked at 256f
s
digital supply voltage (4.5 to 5.5 V)
digital ground
TTL level output (3-state); in normal mode this pin outputs data from the serial interface; in
standby mode, this output is high impedance
TTL level input/output; serial interface word select signal; in master mode (SLAVE = LOW),
this pin outputs the serial interface word select signal; in slave mode (SLAVE = HIGH), this pin
is the word select input to the serial interface; in standby mode (STDB = LOW) this pin is
always an input (high impedance); for polarity: see Table 1
TTL level input/output; in master mode (SLAVE = LOW) the pin outputs the serial interface bit
clock; in slave mode (SLAVE = HIGH) this pin is the input for the external bit clock; data on
SDO is clocked out on the HIGH-to-LOW transition of SCK; the data is valid on the
LOW-to-HIGH transition
Test 1; TTL level input with internal pull-down; in slave mode (slave = HIGH), this pin is used
to select extra serial interface formats (see Table 2)
TTL level input; this input is used to enable the internal high-pass filter when HIGH; in
scan-test mode (TESTB = LOW and TEST1 = LOW) this pin functions as ‘scan chain c’ input
Test B; CMOS level input with internal pull-up; in normal applications, this input should be left
HIGH
analog ground; this pin is internally connected to V
SS
via the on-chip substrate contacts
current reference generator output; 33 k
in parallel with 22 nF is connected from this pin to
V
SSA
right channel analog reference output voltage (
1
2
V
DDA
)
buffer operational amplifier inverting input for right channel
buffer operational amplifier output for right channel
negative 1-bit DAC reference voltage input, connected to 0 V
positive 1-bit DAC reference voltage input, connected to +5 V
buffer operational amplifier output for left channel
buffer operational amplifier inverting input for left channel
left channel analog reference output voltage (
1
2
V
DDA
)
analog supply voltage (4.5 to 5.5 V)
STDB
2
OVLD
3
CKIN
V
DDD
V
SSD
SDO
4
5
6
7
SWS
8
SCK
9
TEST1
10
HPEN
11
TESTB
12
V
SSA
I
ref
13
14
V
refR
BIR
BOR
V
DACN
V
DACP
BOL
BIL
V
refL
V
DDA
15
16
17
18
19
20
21
22
23
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