參數(shù)資料
型號: SAA7139
廠商: NXP Semiconductors N.V.
英文描述: The Digital Video Decoder/Encoder Modules(數(shù)字視頻譯碼器/編碼器模塊)
中文描述: 數(shù)字視頻解碼器/編碼器模塊(數(shù)字視頻譯碼器/編碼器模塊)
文件頁數(shù): 27/53頁
文件大?。?/td> 456K
代理商: SAA7139
Module System: 7128MOD2
Philips Semiconductors
27
Application Note
AN 97085
Video Programming
System Data Inser-
tion
54H - 59H
VPSEN set to high enables the insertion of data for Video Programming
System.
Five bytes VPS5, VPS11, VPS12, VPS13, and VPS14 can be loaded acc.
to the specification of VPS
This register defines the absolute subcarrier phase w.r.t. the synchroniza-
tion pulse scheme. Although in practice the absolute subcarrier phase is
almost never relevant, values for the most common standards NTSC-M
and European PAL are given. Please note that the value is different when
the internal color bar function is active.
These registers directly influence the amplitude of the internal color diffe-
rence baseband signals and thus of the generated subcarrier for quadra-
ture modulated standards (for SECAM, the frequency deviation is
influenced!)
Usually, the nominal settings given in the datasheet should be used; in
case that an analog post filter contributes noticeable attenuation around
the subcarrier frequency, both GAINU and GAINV should be enlarged
accordingly.
Note that the sign bit (0=positive, 1=negative) is located in 5DH for GAINU
and in 5EH for GAINV.
This parameter adds a certain offset to the luminance signal w.r.t. to the
sync tip, but leaves the peak-peak amplitude unaffected.
IF DECOE=high, the odd/even information can be received from a deco-
der supporting this function.
If DECPH=high, a subcarrier oscillator phase reset initiated on the decoder
side will reset the phase of the encoder oscillator.
This parameter adds a certain offset to the luminance blanking level w.r.t.
the sync tip.
Note that this parameter has to be set twice, i.e. outside (5EH) and inside
(5FH) the vertical blanking interval. Usually, both blankings are identical.
Always program with 00H in order to avoid unexpected effects
(0): configures the internal pixel counter either to 858 pixels/line (high) or
868 pixels/line (low)
(1): this bit set to high enables the PAL specific process of inverting the V
color difference component line by line.
(2): usually set to high for standard-compliant chroma bandwidth; in some
cases (e.g. for best S-Video quality), it can be set to low.
(3): this bit set to high enables the SECAM processing; it overrides bit PAL
(4): this bit selects one of two possible gain factors for the luminance
black-to-white amplitude; when set to high, luminance is adjusted for 92.5
IRE output amplitude, and when set to low for 100 IRE output amplitude.
(5): only relevant when RTCE bit is high; usually set to low.
(6): if set to high, internally a constant code corresponding to the lowest
possible output voltage at the DACs for CVBS, Y/C is applied.
(7): if set to high,internally a constant code corresponding to the lowest
possible output voltage at the DACs for R, G, B is applied.
Chroma Phase
5AH
Gain_U, Gain_V
5BH - 5EH
Black Level
5DH
Real Time Control
5DH - 5EH
Blanking Level
5EH - 5FH
NULL
60H
Standard Control
61H
Function
SubAdr
Description
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SAA7146 制造商:未知廠家 制造商全稱:未知廠家 功能描述: