參數(shù)資料
型號: SAA7139
廠商: NXP Semiconductors N.V.
英文描述: The Digital Video Decoder/Encoder Modules(數(shù)字視頻譯碼器/編碼器模塊)
中文描述: 數(shù)字視頻解碼器/編碼器模塊(數(shù)字視頻譯碼器/編碼器模塊)
文件頁數(shù): 25/53頁
文件大?。?/td> 456K
代理商: SAA7139
Module System: 7128MOD2
Philips Semiconductors
25
Application Note
AN 97085
5.2
Summary of Registerfunctions
In the following table the usage of registers is described in order to get a quick view of the most important
functions and give help for programming the device. The table does not contain whole information about the
function or determination of values but should give background information. The subaddress is the location
according to the described function but not exclusive in every case. For further details see chapter ’Slave Recei-
ver’ in the datasheet.
TABLE 5 Registers of the SAA7128/29
Function
SubAdr
Description
Status byte (read
only)
NULL
00H
01H - 25H
Always program with 00H in order to avoid unexpected effects
WSSON enables or disables completely the WSS encoding; for meaning
of the individual bits refer to the table given in ETS-300 294
If RTCE is set to high, Real Time Control (RTC) of the generated subcar-
rier frequency is enabled. RTC should be used whenever the clock for the
video encoder is generated by a digital line-locked video decoder to
ensure stable encoding phase for clean colors.
From a decoder supporting the new function DECCOL, a flag indicating
that color was detected can be received if DECCOL=high.
If DECFIS=high, the field frequency information detected by a decoder can
be received.
Wide Screen Signal
26H - 27H
Real Time Control
28H
Burst Start / End
28H - 29H
The begin and the end of the color burst can be adjusted in a certain range
at an accuracy of LLC clock cycles; the suggested defaults should be used
CG19-CG0: LSB’s of the respective bytes are encoded immediately after
run-in, the MSB’s of the respective bytes have to carry the CRCC bits, in
accordance with the definition of Copy Generation Management System
encoding format.
CGEN set low disables the insertion.
All DAC outputs can be set individually to high impedance through bits
BTRI (Blue or Cb), GTR (Green or Y), RTRI( Red or Cr) YTRI( VBS or
CVBS), CVBSTRI (CVBS or CSYNC).
If CVBSEN0 is set low, the C signal is directed to the DAC normally used
for this signal; if CVBSEN0 is set high, a CVBS signal is directed to this
DAC as an alternative.
If CVBSEN1 is set low, the VBS signal is directed to the DAC normally
used for this signal; if CVBSEN1 is set high, a CVBS signal is directed to
this DAC as an alternative.
Always program with 00H in order to avoid unexpected effects
Common practice is to set GY=GCD in order to adjust both luminance con-
trast and color saturation, when RGB output mode is chosen.
The suggested nominal values given in the datasheet are based on the
proposed external resistor circuitry (23 Ohm series, 75 Ohm load).
Copy Generation
2AH - 2CH
Output Port Control
2DH
NULL
2EH - 37H
Gain Luma and Gain
Colour Diff. of RGB
38H - 39H
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