參數(shù)資料
型號(hào)： SAA7139
廠商： NXP Semiconductors N.V.
英文描述： The Digital Video Decoder/Encoder Modules(數(shù)字視頻譯碼器/編碼器模塊)
中文描述： 數(shù)字視頻解碼器/編碼器模塊（數(shù)字視頻譯碼器/編碼器模塊）
文件頁(yè)數(shù)： 17/53頁(yè)
文件大小： 456K
代理商： SAA7139
Module System: 7128MOD2
Philips Semiconductors
17
Application Note
AN 97085
3.
Interfacing Input Data with a Y-module
The following drawings show some principal ways how to connect a Chameleon Digital Video Encoder to one or
two video/overlay data sources.
Within SAA7128/29 (eventually within a device indicated here as SAA7138/39), the two video data streams can
be directed separately to RGB outputs and Y/C/CVBS outputs. A hard keying or versatile chroma keying and
fading is available for combing both data streams
Mode 1:
Clock LLC comes from SAA7111A (or a similar Philips Digital Video Decoder), the SAA7128/29 video encoder is
slaved to the sync code (frame sync) embedded into the CCIR-656 data stream from SAA7111A. Output H - sync
and V- sync from SAA7128/29 master a memory controller and memory for output of overlay data. Memory con-
troller and associated memory can also be considered to be represented by the OSD/overlay part of an MPEG
decoder.
The two data streams, one from SAA7111A, the second from the overlay generator, are multiplexed to a physical
54 MHz data stream, using LLC as a control signal for the external multiplexer.
Mode 2:
The on-chip LLC clock generator of SAA7128/29 is used to clock the MPEG decoder and the memory, providing
OSD/overlay signals. Both MPEG decoder and separate overlay source are slaves of SAA7128/29 H- and V-
syncs.
This seems to be a rather uncommon configuration, in practice Mode 3 will be more of interest.
Mode 3:
LLC clock is coming from the on-chip crystal oscillator of SAA7128/29, which should be able to be fine-tuned in a
certain range. (LLC could also come from an external oscillator of similar properties). The MPEG decoder is sla-
ved to SAA7128/29 w.r.t. H- sync and V- sync.
A 54 MHz multiplexed data stream, carrying e.g. video with overlay data at the rising clock edge and video wit-
hout overlay data at the falling clock edge, is directly fed to the 54 MHz input port of SAA7128/29.
Mode 4:
As the device indicated here SAA7138/39 has two separate 8 bit D1 ports, MP' and VP', external demultiplexing
is not necessary.
The video decoder SAA7111A is master for the video encoder w.r.t. LLC clock and H-sync and V-sync (embed-
ded frame sync in the CCIR-656 data coming out of the video decoder and going into VP input).
The encoder-internal clock chip buffers the clock as LLCOUT for the OSD/overlay source. SAA7138/39 is sync
master for the OSD/overlay source, which is sending its data to the MP input.
Again, this configuration seems to be uncommon (for test purposes, only), and Mode 5 should be focused on the
more.
Mode 5:
Again, the video decoder SAA7111A is clock and sync master for SAA7138/39, providing clock LLC to clock
input LLC_1, and video and sync via input port VP.
Through H- and V- sync coming out of SAA7138/39, additional OSD/overlay data can be taken from the MPEG
decoder in order to overlay it to the (digitized) analog video. In this case, LLCOUT for the MPEG decoder is
derived from LLC_1. The OSD/overlay data can come with the rising or falling edge of LLCOUT or with both
edges.
If the active video source is MPEG video, the SAA7111A video decoder will idle, and clock for SAA7138/39 is
LLCO, fed to the LLC_2 input of the encoder-internal clock multiplexer. For this operational mode, also the on-
chip crystal oscillator instead of an external oscillator could be used.
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