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參數(shù)資料
| 型號： | SAA7129H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | Digital video encoder |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP44 |
| 封裝： | 10 X 10 X 1.75 MM, PLASTIC, SOT-307-2, QFP-44 |
| 文件頁數(shù)： | 20/56頁 |
| 文件大?。?/td> | 192K |
| 代理商： | SAA7129H |
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2000 Mar 08
20
Philips Semiconductors
Product specification
Digital video encoder
SAA7128H; SAA7129H
Table 16
Subaddress 3AH
Table 17
Subaddresses 42H to 44H and 48H to 4AH
Table 18
Subaddresses 45H to 47H and 4BH to 4DH
BIT
SYMBOL
DESCRIPTION
7
CBENB
0 = data from input ports is encoded; default state after reset
1 = colour bar with fixed colours is encoded
These 2 bits are reserved; each must be set to a logic 0.
6
5
4
SYMP
0 = horizontal and vertical trigger is taken from RCV2 and RCV1 respectively; default
state after reset
1 = horizontal and vertical trigger is decoded out of “ITU-R BT656”compatible data at
MPEG port
0 = YC
B
C
R
-to-RGB dematrix is active; default state after reset
1 = YC
B
C
R
-to-RGB dematrix is bypassed
0 = CVBS output signal is switched to CVBS DAC; default state after reset
1 = advanced composite sync is switched to CVBS DAC
0 = input data is 2’s complement from MPEG port fader input
1 = input data is straight binary from MPEG port fader input; default state after reset
0 = input data is 2’s complement from Video port fader input
1 = input data is straight binary from Video port fader input; default state after reset
3
DEMOFF
2
CSYNC
1
MP2C
0
VP2C
ADDRESS
BYTE
DESCRIPTION
42H
48H
43H
49H
44H
4AH
KEY1LU
KEY1UU
KEY1LV
KEY1UV
KEY1LY
KEY1UY
Key colour 1 lower and upper limits for U, V and Y. If MPEG input signal is within the
limits of key colour 1 the incoming signals at the Video port and MPEG port are added
together according to the equation:
FADE1
×
video signal + (1
FADE1)
×
MPEG signal
Default value of all bytes after reset = 80H.
ADDRESS
BYTE
DESCRIPTION
45H
4BH
46H
4CH
47H
4DH
KEY2LU
KEY2UU
KEY2LV
KEY2UV
KEY2LY
KEY2UY
Key colour 2 lower and upper limits for U,V and Y. If MPEG input signal is within the
limits of key colour 2 the incoming signals at the Video port and MPEG port are added
together according to the equation:
FADE2
×
video signal + (1
FADE2)
×
LUT values
Default value of all bytes after reset = 80H.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA7130 | PCI video broadcast decoder |
| SAA7134 | PCI audio and video broadcast decoder |
| SAA7135 | Single-chip, analog TV video/stereo DECODER |
| SAA7139 | The Digital Video Decoder/Encoder Modules(數(shù)字視頻譯碼器/編碼器模塊) |
| SAA7138 | The Digital Video Decoder/Encoder Modules(數(shù)字視頻譯碼器/編碼器模塊) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7129H/V1,518 | 功能描述:IC DIGITAL VIDEO DECODER 44QFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| SAA7129H/V1,557 | 功能描述:IC DIGITAL VIDEO ENCODER 44-QFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| SAA7129HB | 制造商:NXP Semiconductors 功能描述: |
| SAA7130 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:PCI video broadcast decoder |
| SAA7130HL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:PCI video broadcast decoder |
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