- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372113 > SAA7129H (NXP SEMICONDUCTORS) Digital video encoder PDF資料下載
參數(shù)資料
| 型號： | SAA7129H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | Digital video encoder |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP44 |
| 封裝： | 10 X 10 X 1.75 MM, PLASTIC, SOT-307-2, QFP-44 |
| 文件頁數(shù)： | 31/56頁 |
| 文件大小： | 192K |
| 代理商： | SAA7129H |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當(dāng)前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁
2000 Mar 08
31
Philips Semiconductors
Product specification
Digital video encoder
SAA7128H; SAA7129H
Table 52
Subaddress 6CH
Table 53
Subaddress 6DH
Table 54
Subaddress 6EH
Table 55
Selection of phase reset mode
BIT
SYMBOL
DESCRIPTION
7 to 0
HTRIG[7:0]
These are the 8 LSBs of the 11-bit code that sets the horizontal trigger phase related to
the signal on RCV1 or RCV2 input. The 3 MSBs are held in subaddress 6DH, see
Table 53. Values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed. Increasing
HTRIG[10:0] decreases delays of all internally generated timing signals. Reference
mark: analog output horizontal sync (leading slope) coincides with active edge of RCV
used for triggering at HTRIG[10:0] = 4FH (79).
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
1
0
HTRIG10
HTRIG9
HTRIG8
VTRIG4
VTRIG3
VTRIG2
VTRIG1
VTRIG0
These are the 3 MSBs of the horizontal trigger phase code; see Table 52.
Sets the vertical trigger phase related to signal on RCV1 input. Increasing VTRIG
decreases delays of all internally generated timing signals, measured in half lines;
variation range of VTRIG[4:0] = 0 to 31 (1FH).
BIT
SYMBOL
DESCRIPTION
7
SBLBN
0 = vertical blanking is defined by programming of FAL and LAL; default state after reset
1 = vertical blanking is forced in accordance with “ITU-R BT.624”(50 Hz) or RS170A
(60 Hz)
0 = encoder in normal operation mode
1 = output signal is forced to blanking level; default state after reset
These 2 bits select the phase reset mode of the colour subcarrier generator;
see Table 55.
6
BLCKON
5
4
3
2
1
0
PHRES1
PHRES0
LDEL1
LDEL0
FLC1
FLC0
These 2 bits select the delay on luminance path with reference to chrominance path;
see Table 56.
These 2 bits select field length control; see Table 57.
PHRES1
PHRES0
DESCRIPTION
0
0
1
1
0
1
0
1
no reset or reset via RTCI from SAA7111 if bit RTCE = 1; default value after reset
reset every two lines or SECAM specific if bit SECAM = 1
reset every eight fields
reset every four fields
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA7130 | PCI video broadcast decoder |
| SAA7134 | PCI audio and video broadcast decoder |
| SAA7135 | Single-chip, analog TV video/stereo DECODER |
| SAA7139 | The Digital Video Decoder/Encoder Modules(數(shù)字視頻譯碼器/編碼器模塊) |
| SAA7138 | The Digital Video Decoder/Encoder Modules(數(shù)字視頻譯碼器/編碼器模塊) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7129H/V1,518 | 功能描述:IC DIGITAL VIDEO DECODER 44QFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| SAA7129H/V1,557 | 功能描述:IC DIGITAL VIDEO ENCODER 44-QFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| SAA7129HB | 制造商:NXP Semiconductors 功能描述: |
| SAA7130 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:PCI video broadcast decoder |
| SAA7130HL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:PCI video broadcast decoder |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。