參數(shù)資料
型號(hào)： SAA7114H
廠商： NXP SEMICONDUCTORS
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI data slicer and high performance scaler
中文描述： COLOR SIGNAL DECODER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT407-1, LQFP-100
文件頁數(shù)： 71/147頁
文件大小： 759K
代理商： SAA7114H
2004 Mar 03
71
Philips Semiconductors
Product specification
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI data slicer and high performance scaler
SAA7114
9.6
Host port for 16-bit extension of video data I/O (H port)
The H port pins HPD can be used for extension of the data I/O paths to 16-bit.
The I port has functional priority. If I8_16[93H[6]] is set to logic 1 the output drivers of the H port are enabled depending
on the I port enable control. For I8_16 = 0, the HPD output is disabled.
Table 34
Signals dedicated to the host port
Note
1.
Pin numbers for LQFP100 in parenthesis.
SYMBOL
PIN
(1)
I/O
DESCRIPTION
BIT
HPD7 to HPD0
A13, D12, C12, B12, A12,
C11, B11 and A11
(64 to 67 and 69 to 72)
I/O
16-bit extension for digital I/O
(chrominance component)
IPE[1:0] 87H[1:0], ITRI[8FH[6]]
and I8_16[93H[6]]
9.7
Basic input and output timing diagrams I port
and X port
9.7.1
I
PORT OUTPUT TIMING
The following diagrams illustrate the output timing via the
I port. IGPH and IGPV are logic 1 active gate signals.
If reference pulses are programmed, these pulses are
generated on the rising edge of the logic 1 active gates.
Valid data is accompanied by the output data qualifier on
pin IDQ. In addition invalid cycles are marked with output
code 00H.
The IDQ output pin may be defined to be a gated clock
output signal (ICLK AND internal IDQ).
9.7.2
X
PORT INPUT TIMING
AttheX porttheinputtimingrequirementsarethesameas
those for the I port output. But different to those below:
It is not necessary to mark invalid cycles with a 00H
code
No constraints on the input qualifier (can be a random
pattern)
XCLK may be a gated clock (XCLK AND external XDQ).
Remark
: All timings illustrated in Figs 32 to 38 are given
for an uninterrupted output stream (no handshake with the
external hardware).
Fig.32 Output timing I port for serial 8-bit data at start of a line (ICODE = 1).
IPD[7:0]
IGPH
IDQ
ICLK
00
FF
00
00
SAV
00
CB
Y
CR
Y
00
CB
Y
CR
Y
00
MHB550
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