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參數(shù)資料
| 型號(hào)： | SAA7114H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 顏色信號(hào)轉(zhuǎn)換 |
| 英文描述： | PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI data slicer and high performance scaler |
| 中文描述： | COLOR SIGNAL DECODER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT407-1, LQFP-100 |
| 文件頁(yè)數(shù)： | 69/147頁(yè) |
| 文件大?。?/td> | 759K |
| 代理商： | SAA7114H |
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2004 Mar 03
69
Philips Semiconductors
Product specification
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI data slicer and high performance scaler
SAA7114
9.4.2
X
PORT CONFIGURED AS INPUT
If the data input mode is selected at the expansion port,
then the scaler can select its input data stream from the
on-chip video decoder, or from the expansion port
(controlled by bit SCSRC[1:0] 91H[5:4]). Byte serial
Y-C
B
-C
R
4 : 2 : 2, or subsets for other sampling schemes,
or raw samples from an external ADC may be input (see
also bits FSC[2:0] 91H[2:0]). The input stream must be
accompanied by an external clock (XCLK), qualifier XDQ
and reference signals XRH and XRV. Instead of the
reference signal, embedded SAV and EAV codes
according to ITU 656 are also accepted. The protection
bits are not evaluated.
XRH and XRV carry the horizontal and vertical
synchronization signals for the digital video stream
through the expansion port. The field ID of the input video
stream is carried in the phase (edge) of XRV and state of
XRH, or directly as FS (frame sync, odd/even signal) on
the XRV pin (controlled by XFDV[92H[7]], XFDH[92H[6]]
and XDV[1:0] 92H[5:4]).
The trigger events on XRH (rising/falling edge) and XRV
(rising/falling/both edges) for the scalers acquisition
window are defined by XDV[1:0] 92H[5:4] and
XDH[92H[2]]. The signal polarity of the qualifier can also
be defined (bit XDQ[92H[1]]). Alternatively to a qualifier,
the input clock can be applied to a gated clock (clock gated
with a data qualifier, controlled by bit XCKS[92H[0]]).
In this event, all input data will be qualified.
9.5
Image port (I port)
The image port transfers data from the scaler as well as
from the VBI data slicer, if selected (maximum 33 MHz).
The reference clock is available at the ICLK pin, as an
output, or as an input (maximum 33 MHz). As output, ICLK
is derived from the line-locked decoder or expansion port
input clock. The data stream from the scaler output is
normally discontinuous. Therefore valid data during a
clock cycle is accompanied by a data qualifying (data
valid) flag on pin IDQ. For pin constrained applications the
IDQ pin can be programmed to function as a gated clock
output (bit ICKS2[80H[2]]).
The data formats at the image port are defined in Dwords
of 32 bits (4 bytes), such as the related FIFO structures.
However the physical data stream at the image port is only
16-bit or 8-bit wide; in 16-bit mode data pins HPD7 to
HPD0 are used for chrominance data. The four bytes of
the Dwords are serialized in words or bytes.
Available formats are as follows:
Y-C
B
-C
R
4 : 2 : 2
Y-C
B
-C
R
4 : 1 : 1
Raw samples
Decoded VBI data.
For handshake with the receiving VGA controller, or other
memory or bus interface circuitry, F, H and V reference
signals and programmable FIFO flags are provided. The
information is provided on pins IGP0, IGP1, IGPH and
IGPV. The functionality on these pins is controlled via
subaddresses 84H and 85H.
VBI data is collected over an entire line in its own FIFO,
and transferred as an uninterrupted block of bytes.
Decoded VBI data can be signed by the VBI flag on pin
IGP0 or IGP1.
As scaled video data and decoded VBI data may come
from different and asynchronous sources, an arbitration
scheme is needed. Normally the VBI data slicer has
priority.
The image port consists of the pins and/or signals, as
listed in Table 33.
Forpinconstrainedapplications,orinterfaces,therelevant
timing and data reference signals can also get encoded
into the data stream. Therefore the corresponding pins do
not need to be connected. The minimum image port
configuration requires 9 pins only, i.e. 8 pins for data
including codes, and 1 pin for clock or gated clock. The
inserted codes are defined in close relationship to the
ITU-R BT.656 (D1) recommendation, where possible.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7114H/V2 | 制造商:NXP Semiconductors 功能描述:7114H/V2557 |
| SAA7114H/V2,518 | 功能描述:視頻 IC DIGITAL VIDEO DECODER W/COMB F RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7114H/V2,557 | 功能描述:視頻 IC DECODR W/FILTR RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7114H/V2557 | 制造商:NXP Semiconductors 功能描述:VIDEO DECODER W/FILTER 100LQFP |
| SAA7114H_1 | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Video decoder |
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