參數(shù)資料
型號: SAA7111AH
廠商: NXP SEMICONDUCTORS
元件分類: 消費(fèi)家電
英文描述: Enhanced Video Input Processor EVIP
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: 14 X 14 X 2.70 MM, PLASTIC, QFP-64
文件頁數(shù): 54/72頁
文件大小: 441K
代理商: SAA7111AH
1998 May 15
54
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
17.2.18 S
UBADDRESS
13
Table 33
Output control 3 SA 13
FUNCTION
BIT NAME
LOGIC LEVEL
CONTROL BIT
Bypass control LOW for VPO7 to VPO0
No bypass
BCLO1
BCLO0
BCLO1
BCLO0
BCLO1
BCLO0
BCLO1
BCLO0
0
0
0
1
1
0
1
1
D1
D0
D1
D0
D1
D0
D1
D0
Permanent bypass
Bypass controlled by V_GATE
Bypass controlled by delayed V_GATE
Bypass control HIGH for VPO15 to VPO8
No bypass
BCHI1
BCHI0
BCHI1
BCHI0
BCHI1
BCHI0
BCHI1
BCHI0
0
0
0
1
1
0
1
1
D3
D2
D3
D2
D3
D2
D3
D2
Permanent bypass
Bypass controlled by V_GATE
Bypass controlled by delayed V_GATE
Clock Reference Output Control
CREF is independent of VREF
CCTR1
CCTR0
CCTR1
CCTR0
CCTR1
CCTR0
CCTR1
CCTR0
0
0
0
1
1
0
1
1
D5
D4
D5
D4
D5
D4
D5
D4
CREF is LOW if VREF = 0
CREF is HIGH if VREF = 0
CREF always = 1
Vertical Reference Output Control (VREF)
Internal VREF
VCTR1
VCTR0
VCTR1
VCTR0
VCTR1
VCTR0
VCTR1
VCTR0
0
0
0
1
1
0
1
1
D7
D6
D7
D6
D7
D6
D7
D6
VREF_CCIR
Programmable V_GATE
Delayed programmable V_GATE
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