參數(shù)資料
型號: SAA7111AH
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: Enhanced Video Input Processor EVIP
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: 14 X 14 X 2.70 MM, PLASTIC, QFP-64
文件頁數(shù): 43/72頁
文件大小: 441K
代理商: SAA7111AH
1998 May 15
43
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
17.2
I
2
C-bus detail
The I
2
C-bus receiver slave address is 48H/49H. Subaddresses 0F, 14, 18, 19, 1D and 1E are reserved; subaddress 01
is reserved for chip version.
17.2.1
S
UBADDRESS
00
Table 11
Chip version SA00; note 1
Note
1.
X = reserved.
17.2.2
S
UBADDRESS
02
Table 12
Analog control 1 SA02; note 1
Notes
1.
2.
Mode select (see Figs 33 to 40).
For modes 0 to 3 use BYPS(SA09,D7) = 0 (chrominance trap active), for modes 4 to 7 use BYPS = 1 (chrominance
trap bypassed).
Table 13
Analog control 1 SA 02, D5 to D3 (see Fig.14)
FUNCTION
LOGIC LEVELS
ID07
ID06
ID05
ID04
ID03
ID02
ID01
ID00
Chip version
V1
V2
0
0
0
0
0
1
1
0
X
X
X
X
X
X
X
X
FUNCTION
(2)
CONTROL BITS D2 TO D0
MODE 2
MODE 1
MODE 0
Mode 0 : CVBS (automatic gain)
Mode 1 : CVBS (automatic gain)
Mode 2 : CVBS (automatic gain)
Mode 3 : CVBS (automatic gain)
Mode 4 : Y (automatic gain) + C (gain channel 2 fixed to GAI2 level)
Mode 5 : Y (automatic gain) + C (gain channel 2 fixed to GAI2 level)
Mode 6 : Y (automatic gain) + C (gain channel 2 adapted to Y gain)
Mode 7 : Y (automatic gain) + C (gain channel 2 adapted to Y gain)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DECIMAL VALUE
UPDATE HYSTERESIS FOR 9-BIT GAIN
CONTROL BITS D5 TO D3
GUDL 2
GUDL 1
GUDL 0
0....
....7
off
0
1
0
1
0
1
±
7 LSB
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