2004 Mar 16
98
Philips Semiconductors
Product specification
PC-CODEC
SAA7108E; SAA7109E
The following deviations from “ITU 656 recommendation”
are implemented at the SAA7108E; SAA7109E image port
interface:
SAV and EAV codes are only present in those lines,
where data is to be transferred, i.e. active video lines, or
VBI raw samples, no codes for empty lines
There may be more or less than 720 pixels between
SAV and EAV
The data content and number of clock cycles during
horizontal and vertical blanking is undefined, and may
be not constant
The data stream may be interleaved with not-valid data
codes, 00H, but SAV and EAV 4-byte codes are not
interleaved with not-valid data codes
There may be an irregular pattern of not-valid data, or
IDQ, and as a result, ‘C
B
- Y - C
R
- Y -’ is not in a fixed
phase to a regular clock divider
VBI raw sample streams are enveloped with SAV and
EAV, like normal video
Decoded VBI data is transported as Ancillary (ANC)
data, two modes:
– direct decoded VBI data bytes (8-bit) are directly
placed in the ANC data field, 00H and FFH codes
may appear in the data block (violation to
ITU-R BT.656)
– recoded VBI data bytes (8-bit) directly placed in ANC
data field, 00H and FFH codes will be recoded to
even parity codes 03H and FCH to suppress invalid
ITU-R BT.656 codes.
There are no empty cycles in the ancillary code or its data
field. The data codes 00H and FFH are suppressed
(changed to 01H or FEH respectively) in the active video
stream, as well as in the VBI raw sample stream (VBI
pass-through). As an option the number range can be
limited further.
Table 62
Signals dedicated to the image port
SYMBOL
PIN
I/O
DESCRIPTION
BIT
IPD7 to
IPD0
E14, D14,
C14, B14,
E13, D13,
C13 and B13
H12
I/O
I port data
ICODE[93H[7]], ISWP[1:0] 85H[7:6]
and IPE[1:0] 87H[1:0]
ICLK
I/O
continuous reference clock at image port,
can be input or output, as output decoder
LLC or XCLK from X port
data valid flag at image port, qualifier, with
programmable polarity;
secondary function: gated clock
horizontal reference output signal, copy of
the horizontal gate signal of the scaler, with
programmable polarity;
alternative function: HRESET pulse
vertical reference output signal, copy of the
vertical gate signal of the scaler, with
programmable polarity;
alternative function: VRESET pulse
general purpose output signal for I port
ICKS[1:0] 80H[1:0] and IPE[1:0]
87H[1:0]
IDQ
H14
O
ICKS2[80H[2]], IDQP[85H[0]] and
IPE[1:0] 87H[1:0]
IGPH
G12
O
IDH[1:0] 84H[1:0], IRHP[85H[1]] and
IPE[1:0] 87H[1:0]
IGPV
F13
O
IDV[1:0] 84H[3:2], IRVP[85H[2]] and
IPE[1:0] 87H[1:0]
IGP1
G13
O
IDG12[86H[4]], IDG1[1:0] 84H[5:4],
IG1P[85H[3]] and IPE[1:0] 87H[1:0]
IDG02[86H[5]], IDG0[1:0] 84H[7:6],
IG0P[85H[4]] and IPE[1:0] 87H[1:0]
IPE[1:0] 87H[1:0]
IGP0
F14
O
general purpose output signal for I port
ITRDY
ITRI
J14
G14
I
I
target ready input signals
port control, switches I port into 3-state