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參數(shù)資料
| 型號： | SAA7109E |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | PC-CODEC |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA156 |
| 封裝： | 15 X 15 MM, 1.15 MM HEIGHT, PLASTIC, SOT-472-1, BGA-156 |
| 文件頁數(shù)： | 74/202頁 |
| 文件大?。?/td> | 983K |
| 代理商： | SAA7109E |
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2004 Mar 16
74
Philips Semiconductors
Product specification
PC-CODEC
SAA7108E; SAA7109E
9.3.2
H
ORIZONTAL SCALING
The overall horizontal scaling factor has to be split into a
binary and a rational value according to the following
input pixel
equation:
where,theparameteroftheprescalerXPSC[5:0] = 1 to 63
and the parameter of VPD phase interpolation
XSCY[12:0] = 300 to 8191 (0 to 299 are only theoretical
values). For example,
1
3.5
is split into
1
4
×
1.14286. The
binary factor is processed by the prescaler, the arbitrary
non-integer ratio is achieved via the variable phase delay
VPD circuitry, called horizontal fine scaling. The latter
calculates horizontally interpolated new samples with a
6-bit phase accuracy, which relates to less than 1 ns jitter
for regular sampling schemes. Together the prescaler and
fine scaler form the horizontal scaler of the SAA7108E;
SAA7109E.
Using the accumulation length function of the prescaler
(XACL[5:0] A1H[5:0]), application and destination
dependent (e.g. scale for display or for a compression
machine), a compromise between visible bandwidth and
alias suppression can be found.
9.3.2.1
Horizontal prescaler (subaddresses
A0H to A7H and D0H to D7H)
The prescaling function consists of an FIR anti-alias filter
stage and an integer prescaler, which together form an
adaptive prescale dependent low-pass filter to balance the
sharpness and aliasing effects.
The FIR pre-filter stage implements different low-pass
characteristics to reduce the anti-alias for downscales in
the range of 1 to
1
2
. A CIF optimized filter is built-in, which
reduces artefacts for CIF output formats (to be used in
combination with the prescaler set to
1
2
scale); see
Table 40.
The function of the prescaler is defined by:
An integer prescaling ratio XPSC[5:0] A0H[5:0] (equals
1 to 63), which covers the integer downscale range
1 to
1
63
An averaging sequence length XACL[5:0] A1H[5:0]
(equals 0 to 63); range 1 to 64
A DC gain renormalization XDCG[2:0] A2H[2:0];
1 down to
1
128
)
The bit XC2_1[A2H[3]], which defines the weighting of
the incoming pixels during the averaging process
– XC2_1 = 0
1 + 1...+ 1 + 1
– XC2_1 = 1
1 + 2...+ 2 + 1.
TheprescalercreatesaprescaledependentFIRlow-pass,
with up to 64 + 7 filter taps. The parameter XACL[5:0] can
be used to vary the low-pass characteristic for a given
integer prescale of
1
XPSC[5:0]
. The user can therewith
decide between signal bandwidth (sharpness impression)
and alias.
The equation for the XPSC[5:0] calculation is:
lower integer of-----------------------
=
Where:
the range is 1 to 63 (
value 0 is not allowed
);
Npix_in = number of input pixel, and
Npix_out = number of desired output pixel over the
complete horizontal scaler.
The use of the prescaler results in a XACL[5:0] and
XC2_1 dependent gain amplification.
The amplification
can be calculated according to the equation:
DC gain = [(XACL[5:0]
XC2_1) + 1]
×
(XC2_1 + 1)
It is recommended to use sequence lengths and weights,
which results in a 2
N
DC gain amplification, as these
amplitudes can be renormalized by the XDCG[2:0]
2
N
controlled
shifter of the prescaler.
The renormalization range of XDCG[2:0] is 1,
1
2
... down
to
1
128
.
Other amplifications have to be normalized by using the
following BCS control circuitry. In these cases the
prescaler has to be set to an overall gain
≤
1, e.g. for an
accumulation sequence of ‘1 + 1 + 1’ (XACL[5:0] = 2 and
XC2_1 = 0), XDCG[2:0] must be set to ‘010’, which
equals
1
4
and the BCS has to amplify the signal to
4
3
(SATN[7:0] and CONT[7:0] value = lower integer of
4
3
×
64).
The use of XACL[5:0] is XPSC[5:0] dependent.
XACL[5:0] must be <2
×
XPSC[5:0].
XACL[5:0] can be used to find a compromise between
bandwidth (sharpness) and alias effects.
H scale ratio
output pixel
=
H scale ratio
XPSC[5:0]
XSCY[12:0]
×
=
XPSC[5:0]
Npix_out
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA7108AE | HD-CODEC |
| SAA7109A | HD-CODEC |
| SAA7109AE | HD-CODEC |
| SAA7110A | Digital Multistandard Colour Decoder(數(shù)字多標(biāo)準(zhǔn)彩色譯碼器) |
| SAA7111A | Enhanced Video Input Processor EVIP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7109E/V1,518 | 功能描述:視頻 IC PC CODEC WO MACROVISION LCNE RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7109E/V1,557 | 功能描述:視頻 IC PC CODEC WO MACROVISION LCNE RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7110 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:One Chip Front-end 1 OCF1 |
| SAA7110/7110A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:One Chip Frontend 1 (OCF1) Product Specification |
| SAA7110A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:One Chip Front-end 1 OCF1 |
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