參數(shù)資料
型號(hào): SAA5355
廠商: NXP SEMICONDUCTORS
元件分類: 顯示控制器
英文描述: Single-chip colour CRT controller FTFROM
中文描述: 40 X 80 CHARACTERS CRT CHAR DSPL CTLR, PDIP40
文件頁(yè)數(shù): 4/31頁(yè)
文件大?。?/td> 335K
代理商: SAA5355
March 1986
4
Philips Semiconductors
Product specification
Single-chip colour CRT controller
(FTFROM)
SAA5355
PINNING
1
2
3
V
SS(1)
BUFEN
RE
Ground (0 V).
Buffer enable input to the 8-bit link-through buffer.
Register enable input. This enables A1 to A6 and UDS as inputs,
and D8 to D15 as input/outputs.
Multiplexed address and data bus input/outputs. These pins also function as the
8-bit link-through buffer.
Ground (0 V).
Analogue reference input.
4 to 19
A16 to A1/
D15 to D0
V
SS(2)
REF
B
G
R
VDS
20
21
22
23
24
25
Analogue outputs (signals are gamma-corrected).
Switching output for dot, screen (row), box and window video data; for use when
video signal is present (e.g. from tv, VLP, alpha
+
photographic layer). This output
is LOW for tv display and HIGH for text and will interface directly with a number of
colour decoder ICs (e.g. TDA3563, TDA3562A).
Output disable causing R, G, B and VDS outputs to go to high-impedance state.
Can be used at dot-rate.
12 MHz clock output for hard-copy dot synchronization (referenced to output
dots).
Sandcastle feedback output for SAA5230 teletext video processor or other circuit.
Used when the display must be locked to the video source (e.g. VLP).
The phase-lock part of the sandcastle waveform can be disabled to allow
free-running of the SAA5230 phase-locked loop.
1,00699 MHz or 6,041957 MHz output.
6,041957 MHz clock input (e.g. from SAA5230). Internal a.c. coupling is provided.
Video composite sync input (e.g. from SAA5230) for phase reference of vertical
display timing when locking to a video source (e.g. VLP) or, in stand-alone sync
mode, output from internal oscillator circuit (fixed frequency).
Text composite sync input/output depending on master/slave status.
Field sync pulse output or defined-display-area flag output (both referenced to
output dots).
Upper data strobe input/output.
Lower data strobe output.
Data transfer acknowledge (open drain output).
Bus request to microprocessor (open drain output).
Address strobe output to external address latches.
Read/write input/output. Also serves as send/receive for the link-through buffer.
Positive supply voltage (
+
5 V).
26
OD
27
CLKO
28
SAND
29
30
31
F1/F6
F6
VCS/OSCO
32
33
TCS
FS/DDA
34
35
36
37
38
39
40
UDS
LDS
DTACK
BR
AS
R/W(S/R)
V
DD
相關(guān)PDF資料
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