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參數(shù)資料
| 型號： | SAA5355 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顯示控制器 |
| 英文描述： | Single-chip colour CRT controller FTFROM |
| 中文描述： | 40 X 80 CHARACTERS CRT CHAR DSPL CTLR, PDIP40 |
| 文件頁數(shù)： | 11/31頁 |
| 文件大小： | 335K |
| 代理商： | SAA5355 |
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March 1986
11
Philips Semiconductors
Product specification
Single-chip colour CRT controller
(FTFROM)
SAA5355
Notes to the characteristics
1.
Pin 30 must be biased externally.
2.
Value under investigation
3.
16-level analogue voltage outputs.
4.
Output voltage guaranteed when programmed for top level.
5.
All timings are related to a 6,00 MHz clock.
6.
CLKO, R, G, B, F1/F6, VDS: C
L
= 25 pF.
FS/DDA: C
L
= 50 pF
7.
CLKO, F1/F6, VDS, FS/DDA: reference levels = 0,8 to 2,0 V
R, G, B: reference levels = 0,8 to 2,0 V with V
REF
= 2,7 V
8.
These times may momentarily be reduced to a nominal 83 ns in slave-sync mode at the moment of
re-synchronization.
9.
C
L
= 150 pF.
10. Reference levels = 0,8 to 2,0 V.
11. Microprocessor write cycle times of less than 500 ns are permitted but often result in Wait States being generated,
the precise timing of DTACK will then depend on the internal synchronization time.
Microprocessor WRITE to FTFROM
(Fig.10)
Write cycle time (note 11)
R/W LOW set-up to UDS fall
RE LOW to UDS fall
Address valid to UDS fall
UDS LOW time
Data valid to UDS rise
UDS LOW to DTACK LOW
UDS HIGH to DTACK rise
UDS HIGH to data hold
UDS HIGH to address hold
UDS HIGH to RE rise
UDS HIGH to R/W rise
t
WCY
t
WUD
t
RES
t
ASS
t
LUS
t
DSS
t
DTA
t
DTR
t
DSH
t
DSA
t
SRE
t
UDW
500
0
30
30
100
80
0
0
10
10
10
0
60
75
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
F1/F6 to memory access cycle
(Fig.11)
UDS HIGH to F6 (component of F1/F6) rise
F6 (component of F1/F6) HIGH to UDS rise
t
UF6
t
F6U
20
40
ns
ns
SYNCHRONIZATION and BLANKING
TCS, SAND, FS/DDA
See Fig.12 for timing relationships
and Fig.13 for vertical sync and
blanking waveforms.
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
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